Logic basic cell

Details Logic basic cell Logic basic cell

2005-02-21

2008-10-07

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S049000, C326S104000

Reexamination Certificate

active

07432736

ABSTRACT:
A logic basic cell contains a first logic function block and a second logic function block for the logic combination of a first input signal and a second input signal in accordance with a predeterminable first or second logic subfunction, and a first logic transistor coupled to the first logic function block, having a gate terminal, at which a third input signal can be provided, and having a source/drain terminal at which the output signal can be provided. Furthermore, a second logic transistor coupled to the second logic function block is provided, having a gate terminal, at which a complementary signal with respect to the third input signal can be provided, and having a source/drain terminal, which is coupled to the source/drain terminal of the first logic transistor.

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Wannemacher, M; “Das FPGA-Kochbuch”; (“The FPGA Cookbook”); figure 6.4: SRAM cell from XILINX, 1st edition, International Thomson Publishing Company, Bonn, 1998, p. 111, no month.
Wannemacher, M; “Das FPGA-Kockbuch” (The FPGA Cookbook); figure 7.36; logic block (CLB) of the XC4000 families, 1st edition, International Thomson Publishing Company, Bonn, 1998, p. 197, no month.

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