Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent
1996-12-31
2000-08-01
Rinehart, Mark H.
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
709210, G06F 1338, G06F 1517
Patent
active
060981342
ABSTRACT:
A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available. A contemporary microprocessor such as a P6 has a deferred transaction protocol to implement split transactions, but this protocol is not available on a PCI bus. Split transactions are done by a "retry" command on a PCI bus, wherein a read request that cannot be completed immediately is queued and a "retry" response is sent back to the requester on the bus; this instructs the requester to retry (send the same command again) at a later time. To avoid a situation where two processors issue locked cycles which are enqueued and retried in separate bridges, a "Superlock" signal is added to the processor bus, which is asserted by a bridge as soon as a locked transaction is enqueued, and thereafter neither bridge will accept a locked cycle issued by a processor, other than that locked read that was initiated by a processor and enqueued in the bridge and is being retried.
REFERENCES:
patent: 5533204 (1996-07-01), Tipley
patent: 5838935 (1998-11-01), Davis et al.
Mano, "Computer System Architecture Third Edition," Prentice Hall, pp. 489, 490, 1993.
Hennesay and Patterson, "Computer Organization and Design, " Morgan Kaufmann Publishers, pp. 594-597, 607, 619, 630, 1994.
Hausauer Brian S.
Michels Peter
Pettey Christopher J.
Seeman Thomas R.
Compaq Computer Corp.
Patru Daniel
Rinehart Mark H.
LandOfFree
Lock protocol for PCI bus using an additional "superlock" signal does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Lock protocol for PCI bus using an additional "superlock" signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lock protocol for PCI bus using an additional "superlock" signal will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-673997