Lock-free bounded FIFO queue mechanism

Details Lock-free bounded FIFO queue mechanism Lock-free bounded FIFO queue mechanism

2008-04-29

2008-04-29

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

Reexamination Certificate

active

11241225

ABSTRACT:
A system includes a processor and a size bounded first-in first-out (FIFO) memory that is connected to the processor and a display is connected to the processor. A managing process to run on the processor to manage the FIFO memory structure. The FIFO memory includes a counter portion and a value portion for each of a tail portion and a head portion, and the managing process is non-blocking. The counter portion is used as a timestamp to maintain FIFO order.

REFERENCES:
patent: 6178473 (2001-01-01), Bonola
patent: 6697927 (2004-02-01), Bonola
patent: 6889269 (2005-05-01), Forin et al.

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