Lock detect circuit for detecting a lock condition in a phase lo

Details Lock detect circuit for detecting a lock condition in a phase lo Lock detect circuit for detecting a lock condition in a phase lo

1993-07-12

1995-02-28

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375376, 327156, H04L 700, H03D 324

Patent

active

053944445

ABSTRACT:
A lock detect circuit (18) determines when a reference frequency and a feedback frequency are frequency locked using a reference counter (32) and a feedback counter (36). The reference counter (32) and the feedback counter (36) are clocked by the reference frequency and the feedback frequency, respectively. After a first period of time, the outputs of the counters are compared. The outputs of the counters are also compared at the end of a second period of time. To be frequency locked, the two count values must be equal at both the end of the first and the second periods of time. A count window is generated from the reference frequency signal to indicate a range of frequencies for which the feedback frequency is locked. Once lock is achieved, the count window is widened such that the feedback frequency is still within a lock range when some aliasing occurs.

REFERENCES:
patent: 3863156 (1975-01-01), Bogert
patent: 4639680 (1987-01-01), Nelson
patent: 4853841 (1989-08-01), Richter
patent: 4876518 (1989-10-01), Perkins
patent: 4929916 (1990-05-01), Fukuda
patent: 4988955 (1991-01-01), Horie
patent: 5008635 (1991-04-01), Hanke et al.
patent: 5126690 (1992-06-01), Bui et al.
patent: 5168245 (1992-12-01), Koskowich
patent: 5173927 (1992-12-01), Strommer
patent: 5260979 (1993-11-01), Parker et al.
patent: 5278702 (1994-01-01), Wilson et al.

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