Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-02-16
2001-09-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Reexamination Certificate
active
06284553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method of manufacturing high performance semiconductor devices. More specifically, this invention relates to a method of inspecting semiconductor devices during manufacturing. Even more specifically, this invention relates to a method of classifying defects identified during the inspection of semiconductor devices. And even more specifically, this invention relates to a method of assigning location dependent classifications to defects identified during the inspection of semiconductor devices.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continually increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects occurring during the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, chips that must be discarded because of a defect increases the cost of the remaining usable chips.
Each semiconductor chip requires numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. In order to etch metal lines, for example, a layer of photoresist is formed on the surface of the semiconductor chips and patterned by developing the photoresist and washing away the unwanted portion of the photoresist. Because the metal lines and other metal structures have “critical” dimensions, that is, dimensions that can affect the performance of the semiconductor chip, the process of forming the photoresist pattern for each layer is examined during the manufacturing process. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits.
In the course of modern semiconductor manufacturing, semiconductor wafers are routinely inspected using “scanning” tools to find defects. The scanning tool determines the location and other information concerning defects that are caught and this information is stored in a data file for later recapture and inspection of any of the defects. These data files are stored in a relational database that has the ability to generate wafer maps with defects shown in their relative positions. The data database typically has the ability to send these wafer map files to various review tools within the manufacturing plant. This is very useful as it allows for re-inspection on various after-scan inspection tools within the manufacturing plant. These inspection tools include Optical Microscopes and Scanning Electron Microscopes (SEMs) that allow for classification of the defects. Images taken on the various after-scan inspection tools can be linked by linkage data to the defect on a wafer map and reviewed at a workstation at the convenience of an engineer or technician.
In order to be able to quickly resolve process or equipment issues in the manufacture of semiconductor products, a great deal of time, effort and money is expended on the capture and classification of silicon based defects. Once caught and properly described, work can begin in earnest to resolve the cause, to attempt elimination, and to determine adverse effects on device parametrics and performance. The over-riding difficulty to date is the training and maintaining a cadre of calibrated human inspectors who classify all defects consistently and without error. One of the frustrations of human classifiers can be attributed to the inability to isolate or extract the defect in question from its original background environment.
In an attempt to overcome this problem, optical scan tools are used to review defects captured by the scan tools and can be programmed to automatically classify the captured defects. For example, an optical scan tool can use a comparative method to isolate defects so they can be classified. The comparative method uses a reference die or cell to “look” for a difference between the reference and the current image. The difference is the so-called defect. The scan tool is often able to detect differences between the reference and current image, which it calls defects, which are not discernable by the human defect classifier.
In the typical automatic defect classification methodology, defects are recaptured and reviewed on an optical review tool and automatically classified. The classification information is sent to a relational database where it can be retrieved by a defect management system for further processing, analysis, off-line viewing, charting and other analysis procedures. However, this classification methodology can not determine whether a defect is a “killer” defect unless the defect is relatively large. This is because certain size or certain type defects on one portion of the die can be a killer defect whereas, on another portion of the die the same defect would not be a killer defect. Each die have various areas that can accommodate different size defects and different types (or classifications) of defects.
Therefore, what is needed is an inspection methodology that would have the capability to correlate captured defects to the different critical areas of the die.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other object and advantages are attained by a method of manufacturing high performance semiconductor integrated devices in which defects are determined to be killer or non-killer defects.
In accordance with an aspect of the invention, a layer on a lot of semiconductor wafers is processed, at least one inspection wafer is selected from the lot of semiconductor wafers and defect information is generated and input to a defect management system. The defects are reviewed on review and classification tools and defect classification information is input to the defect management system. Critical area information for the device and layer is generated and input into the defect management system where the defect classification information is correlated with the critical area information to determine whether each defect is a killer or a non-killer defect.
In another aspect of the invention, the killer or non-killer defect information is tabulated in a defect table and is tabulated according to layer.
In another aspect of the invention, the tabulated defect table information is utilized to determine statistical yield predictions.
The method of the present invention thus effectively provides a semiconductor manufacturing process for the manufacture of high performance integrated circuits that provides location dependent automatic defect classification that can be utilized to provide statistical yield prediction.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized,
Steffan Paul J.
Yu Allen S.
Advanced Micro Devices , Inc.
Nelson H. Donald
Niebling John F.
Stevenson André C
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