Location based timing scheme in memory design

Details Location based timing scheme in memory design Location based timing scheme in memory design

1999-07-08

2002-08-13

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06434736

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of memory design, and more specifically, to a memory having improved access time of instructions or data.
2. Background Information
The performance of a computer system is based, among other factors, on the memory access time. In order to reduce the number of average clock cycles necessary to access the memory, high speed memories may be utilized. A cache memory, as one example of a high speed memory, is used in many computer systems to improve system performance. A cache memory is a relatively small memory which resides either inside the central processor, also referred to as level one (L1) cache memory, or between the processor and the main system memory, also referred to as level two (L2) cache memory.
Caches improve the system performance by storing and supplying frequently used instructions or data in one or two clock cycles rather than two or more clock cycles generally required for a main memory access. The cache performance depends on two factors: access time and hit ratio. The hit ratio is defined as the probability of finding the needed information in the cache, which is a hit, divided by the probability of having to go to the main memory, which is a miss. The cache access time is the maximum time it takes to access the cache on a hit.
Following the conventional memory circuit design, the memory cells of a cache memory are organized into rows and columns. Wordlines are generally associated with rows of memory cells and bitlines are generally associated with columns of memory cells. During a typical memory read operation, the wordline for a particular memory cell to be read is asserted. In memories which use a differential sensing scheme to detect the contents of the memory, a differential is then developed between two bitlines coupled to the memory cell to be read. After the bitline differential has developed to a predetermined differential voltage, the associated sense amplifier can be enabled to read out the information on the selected memory cell.
During a memory operation, the processor anticipates the “worst case timing” memory response to a request for data and times the data transfer accordingly. In other words, for each memory operation, the processor assumes the longest amount of time (i.e. the worst case timing) to complete the operation, even if the memory operation can be completed in a shorter amount of time. Depending on the physical location of the cells in a memory array, the data access time for a read operation can differ between memory locations. In other words, due to the RC delay of the wordlines and bitlines, data belonging to a certain cell location in the memory array may be read faster than data found in other cell locations located farther away from the I/O circuitry. For example, in
FIG. 2
, the data in the cell
2
of the memory array
10
can be accessed faster than the data in the cell
4
. For this example, the access time of data found in memory cell
4
will be referred to as the “worst case read”, while the access time of the data found in memory cell
2
will be referred to as the “best case read”. In conventional memory design, even if data is found in a cell location with a best case read, the sense amplifier is not enabled until the worst case read has achieved a certain bitline differential (i.e. the system presumes the worst case timing).
Thus, a new approach to improving memory read access time is needed which determines the sense amplifier enable time based on the location of the memory cell to be read.
SUMMARY OF THE INVENTION
A method for controlling a sense amplifier enable signal during a read operation in a memory array is described. A subset of address bits is selected from an address of a memory cell to be read. The subset of address bits is representative of a plurality of regions in the memory array. Each region of the plurality of regions comprises a plurality of memory cells. The plurality of regions are determined based on the subset of address bits, wherein each region of the plurality of regions is associated with a distinct region access time requirement. The memory cell of the plurality of memory cells to be read is selected and its corresponding region in the memory array is determined. The sense amplifier enable signal for the memory cell is timed based on the corresponding region access time requirement.
Additional features and benefits of the present invention will become apparent from the detailed description, figures, and claims set forth below.


REFERENCES:
patent: 6028810 (2000-02-01), Ooishi

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