Locally folded split level bitline wiring

Details Locally folded split level bitline wiring Locally folded split level bitline wiring

1999-10-04

2001-09-18

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S241000, C438S258000, C438S618000, C438S620000, C438S622000, C438S625000, C438S626000, C438S631000, C438S633000, C438S637000, C438S638000

Reexamination Certificate

active

06291335

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to semiconductor layouts and more particularly, to a method for wiring semiconductor devices which includes providing a local split level bitline wiring scheme with reduced contact levels.
2. Description of the Related Art
Semiconductor memories typically include an array of memory cells disposed in rows and columns. Rows and columns are generally defined by wordlines and bitlines which are used to access the memory cells. Bitlines generally are employed for reading and writing data to and from the memory cells. For dynamic random access memory cells (DRAMs), it is desirable for the bitline pairs to be included in a structure that reduces noise between the bitline pairs during operation.
One method for reducing noise includes a folded bitline scheme. This means that an active bitline is neighbored by a passive bitline which serves as a reference bitline during read/write cycles. The folded bitline structure is relatively easy to implement in a horizontal arrangement. This horizontal arrangement cannot be easily extended to structures where two metal layers are employed for alternating bitlines, especially for sub-8F
2
memory cells (where F is a minimum feature size for a given technology).
In one conventional architecture, a globally folded bitline scheme has been attempted. In the globally folded bitline scheme, two neighboring bitlines each include a same number of memory cells, globally. Locally however, the next neighboring memory cells of a given bitline do not belong to the adjacent bitline. Instead, neighboring memory cells are, for the most part, connected to the same bitline. This scheme is a non-optimized arrangement for the bitlines, especially from a noise minimization standpoint.
Referring to
FIG. 1
, a globally folded bitline structure
10
is shown. Structure
10
includes a first layer
12
and a second layer
14
. The first layer
12
and second layer
14
include alternating portions
13
of bitlines
16
, and may be referred to as a twisted bitline architecture. Bitlines
16
include a first bitline BL
1
and a second bitline BL
2
. BL
1
and BL
2
alternate positions between the first layer
12
and the second layer
14
. BL
2
is employed as a reference for BL
1
(and vice versa). The reference bitline (e.g. BL
2
) does not connect to cells
18
in the vicinity of the cells
18
of a given bitline (e.g., BL
1
). Instead, a group of cells
22
are connected to BL
1
, and another group of cells
24
are connected to BL
2
. Since neighboring cells of each group connect to the same bitline, noise is easily introduced. In other words, all the cells of the group
22
connect to BL
1
while all the cells of the group
24
are connected to BL
2
.
Referring to
FIG. 2
, a schematic representation of a locally folded bitline arrangement or structure
100
is shown. Structure
100
includes a first bitline
102
and a second bitline
104
. First bitline
102
is formed in a first layer
106
and second bitline
104
is formed in a second layer
108
. Bitlines
102
and
104
do not alternate positions between layers as described above. Instead, each bitline
102
connects to every other memory cell
110
, and bitline
104
connects to memory cells
110
adjacent to the memory cells connected to by bitline
102
. In this way, nearest neighbor cells are each connected to different bitlines. Each bitline
102
and
104
acts as a reference for the other of bitlines
102
and
104
to reduce noise within signals traveling along bitlines
102
and
104
during read/write cycles, for example. However, providing two-level bitline wiring is often challenging due to the need for additional contact space and processes.
Referring to
FIG. 3
, a cross-sectional view of a conventional split level bitline wiring scheme is shown for a dynamic random access memory device
120
. Device
120
includes a silicon substrate
122
. Substrate
122
primarily includes two main regions, an array region
124
and a support region
126
. Array region
124
includes a plurality of memory cells each including a gate structure
128
for an access transistor
130
for accessing a storage capacitor (not shown) in substrate
122
. Contacts
132
and
134
are employed to connect diffusion regions
136
of access transistors to bitlines
138
and
140
. Bitlines
138
and
140
are on different levels.
In support region
126
, logic devices and other support circuitry are provided. A transistor
142
includes a gate structure
144
. A contact
146
connects to gate structure
144
while a contact
148
connects to a diffusion region
150
of transistor
142
. Contacts
146
and
148
are later connected to an upper metal layer
152
by contacts
154
. Contacts
146
and
148
are bordered contacts. Contacts
132
,
134
,
146
and
148
are formed in four different processes as indicated in squares with numbers 1-4. Contact
132
is formed in a first contact forming process. Contacts
146
and
148
are formed in a second contact forming process. Contact
134
to a second metal layer is formed in a third contact forming process. Contacts
154
are formed in a fourth contact forming process.
Therefore, a need exists for a locally folded bitline arrangement for a multiple level bitline wiring scheme which includes fewer processing steps. A further need exists for a method for providing the locally folded bitline structure with a layout area savings.
SUMMARY OF THE INVENTION
A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts are formed between first level bitlines in the array region and a first portion of the first contacts, while forming second contacts to a first metal layer from the gate structures and diffusion regions in the support region. Third contacts are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer from the first metal layer in the support region.
A method for fabricating a dynamic random access memory with a twisted split level folded bitline structure consisting of three contact levels includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts to diffusion regions between the gate structures in the array region are formed. The first contacts have a height which is substantially the same for all first contacts. A first dielectric layer is patterned over the gate structures in the array region and the support region. Second contacts are formed between first level bitlines in the array region and a first portion of the first contacts, while forming second contacts to a first metal layer from the gate structures and diffusion regions in the support region. The second contacts are formed through the first dielectric layer. A second dielectric layer is patterned over the first level bitlines in the array region and the first metal layer in the support region. Third contacts are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer from the first metal layer in the support region. The third contacts are formed through the second dielectric layer.
In alternate methods, the first contacts are preferably borderless contacts. The first level bitlines and first metal line may be included on an M
0
layer, and the second level bitlines and second metal line may be included on an M
1
layer. The first level bitlines may function as an electrical reference for the second level bitlines, and the second level bitlines may function as an electrica

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