Localized split floating gate device using drain coupling to...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S314000, C257S316000, C257S320000, C257S321000, C257S322000, C257S326000

Reexamination Certificate

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06998671

ABSTRACT:
The present invention provides a method for using drain coupling to suppress the second bit effect of localized split floating gate devices. By suitably designing the gate and drain overlap region, the drain coupling coefficient can be controlled to effectively suppress the second bit effect during a reverse read operation. The modified reverse read method such as the “raised source voltage VS” method can also be employed to further improve the drain coupling effect without read disturb. Furthermore, the drain coupling can improve the channel hot electron (CHE) injection efficiency.

REFERENCES:
patent: 5877523 (1999-03-01), Liang et al.
patent: 6624025 (2003-09-01), Hsieh et al.

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