Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-24
2003-06-03
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000
Reexamination Certificate
active
06573554
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to development of semiconductor structures and in particular to development of semiconductor container structures using localized masking techniques.
BACKGROUND
Semiconductors are used extensively in today's electronic devices. Their miniature size and low power requirements enable highly complex circuits to be used in places never before thought possible. This has led to the development of systems with the speed and power to make our lives easier without encumbering us with bulky boxes and power-hungry electronics. One of the keys to both light weight and energy efficiency is the tiny size of the circuitry. With each new generation of circuit technology, comes smaller and smaller device sizes.
Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor includes two conductive plates. The top plate of each capacitor is typically shared, or common, with each of the other capacitors. This plate is referred to as the “top cell plate.” The charge stored across the capacitor is representative of a data bit and can be either a high voltage or a low voltage.
Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as digit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. Thus, each such memory cell has two digit lines, digit and digit complement.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line decoder and to a digit line decoder. The word line decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The digit line decoder selects a digit line pair in response to the digit line address. For a read operation, the selected word line activates the access transistors for a given word line address, and data is latched to the digit line pairs.
Some circuit devices utilize “container” structures, and such container structures are often utilized as a capacitor for a memory cell due to their efficient use of semiconductor die real estate. After formation, these container structures look like tiny holes within the surrounding material. They will generally have a closed bottom, an open top and sidewalls extending between the closed bottom and open top. Typically, containers that will be formed into capacitor structures will have dimensions that are taller than they are wide, often referred to as a “high aspect-ratio.” This high aspect-ratio of container capacitors can allow the capacitor to store more energy while maintaining the same two-dimensional surface area. Conversely, the diameter of the hole can be reduced with no impact on energy storage to reduce the required surface area for the device. This allows for faster, smaller, and more energy-efficient devices to be constructed.
In order to further increase a container capacitor's ability to store energy, semiconductor manufacturers have moved towards a technology using hemispherical grain (HSG) polysilicon. HSG polysilicon processing provides a roughened surface, with individual grains of polysilicon protruding from the surface of the film inside the container, thereby increasing the effective surface area of the capacitor formed of the container. The combination of using high aspect-ratio structures and HSG polysilicon has produced semiconductors with much higher performance characteristics than previous structures, while maintaining the same amount of die real estate.
HSG polysilicon processing typically involves a blanket formation of HSG polysilicon over the entire surface of the supporting structure in which the containers are formed. Since the surface HSG polysilicon must be removed to define the individual container capacitors, this progression in technology has also introduced new problems to overcome, i.e., removal of unwanted HSG polysilicon while minimizing the introduction of defects caused by the removal process.
For example, container capacitors are usually formed in an insulating material, such as borophosphosilicate glass (BPSG). Next, traditional Low Pressure Chemical Vapor Deposition (LPCVD) processing deposits an HSG polysilicon layer over the entire support structure, including the inside of the container capacitor hole and as well as the entire surface of the support structure. The processing may also form HSG polysilicon on the backside of the support structure.
The HSG polysilicon on the surface and/or backside of the support structure is undesirable in the creation of container capacitors. The traditional method of removing the undesired HSG polysilicon uses a planarization process such as chemical-mechanical planarization (CMP). However, concern has arisen over the fact that the CMP process itself may inherently cause defects such as chatter marks, scratches, residue and CMP-related particle defects that are left as a result of the slurry. These defects may produce performance characteristics making the semiconductor structures unusable or of questionable quality and reliability.
Another concern of the CMP process is that grains of an HSG polysilicon surface are fragile and can become dislodged during the mechanical planarization process. A dislodged HSG polysilicon grain that bridges between two container capacitors may cause a cell-to-cell short leading to charge leakage and resultant improper performance. To help protect against such failures, cell formation processing includes the use of a fill material to mask and protect the container holes during CMP removal of surface HSG, as well as during subsequent removal of the surrounding BPSG. However, such techniques are not entirely effective against the mechanical strains induced by CMP.
A method of forming a patterned seed layer in trenches has been proposed by Schinella et al. in U.S. Pat. No. 5,670,425 issued Sep. 23, 1997. Schinella et al. relates to the forming of local area interconnects in an integrated circuit structure by selective deposition of certain conductive metal compounds over a seed layer previously formed in one or more trenches in an insulation layer wherein the one or more trenches have been previously formed in a pattern conforming to the desired interconnect configuration, so that the objectionable step of patterning a blanket deposited layer of a conductive metal compound can be eliminated. In accordance with one embodiment of the invention of Schinella et al., Schinella et al. propose a process in which a photoresist layer may be formed over an insulation layer and a seed layer thereon which will flow into coated trenches as well as over the portions of the seed layer deposited over the top surface of the insulation layer, forming a planar layer of photoresist. Schinella et al. then propose, in one embodiment, that to expose those portions of the seed layer not on a trench surface, the photoresist layer could be partially exposed to light energy (to only expose the top portion of the photoresist layer), and then conventionally developed to remove such exposed top portions of the photoresist layer. The seed layer of Schinella et al. normally may comprise any electrically condu
Mercaldi Garry A.
Yates Donald L.
Jackson Jerome
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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