Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-09-11
2004-11-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S421000, C257S659000, C257S775000, C365S158000, C365S171000, C365S173000
Reexamination Certificate
active
06822278
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to magnetic memory devices, and more particularly, to field-inducing line configurations arranged adjacent to magnetic cell junctions.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
Recently, advancements in the use of magneto-resistive materials have progressed the development of magnetic random access memory (MRAM) devices to function as viable non-volatile memory circuits. In general, MRAM circuits exploit the electromagnetic properties of magneto-resistive materials to set and maintain information stored within individual magnetic memory cell junctions of the circuit. In particular, MRAM circuits utilize magnetization direction to store information within a memory cell junction, and differential resistance measurements to read information from the memory cell junction. Typically, an MRAM device includes a plurality of conductive lines with which to generate magnetic fields such that the magnetic direction of one or more memory cell junctions may be changed or oriented. Consequently, the conductive lines may also be referred to as “field-inducing lines.” In some cases, the conductive lines may be referred to as “bit” and “digit” lines. Generally, “bit” lines may refer to conductive lines arranged in contact with memory cell junctions that are used for both write and read operations of the memory cell junctions. “Digit” lines, on the other hand, may refer to conductive lines spaced adjacent to the memory cell junctions that are used primarily during write operations of the memory cell junctions.
Typically, bit lines and digit lines are formed as substantially straight and contiguous structures of metal having uniform widths. In most cases, it is desirable to fabricate a field-inducing line with a relatively low amount of resistivity. As such, bit lines and digit lines typically include a single bulk material such as, aluminum or copper, for example. In some cases, the conductive lines may further include a magnetic cladding layer, such as nickel-iron or cobalt-iron, to concentrate a magnetic field in a particular direction. In general, a “cladding layer,” as used herein, may refer to a metal sheathe used to cover or line a portion of a metal structure. Typically, the placement of a cladding layer within a field-inducing line of a magnetic memory cell device may be along the surfaces of the bit lines and/or digit lines farthest away from the magnetic cell junctions of the device. For example, in an embodiment in which a conductive line is arranged above a memory cell junction, a cladding layer may comprise the sidewalls and upper surface of the conductive line. However, in an embodiment in which a conductive line is alternatively or additionally arranged below the memory cell junction, a cladding layer included within such a lower conductive line may comprise the sidewalls and lower surface of the conductive line. In this manner, the magnetic cladding layer included within the bit and/or digit lines of a magnetic memory cell device may advantageously focus a generated magnetic field toward a memory cell junction. As a result, the magnetic direction of the memory cell junction may be more easily oriented.
Unfortunately, in some cases, the combination of an aluminum structure with a cladding layer may prove to be difficult to fabricate. In particular, forming a reliable device with an aluminum field-inducing line having a cladding layer below a memory cell junction is generally very difficult. Typically, an aluminum line is patterned rather than formed by the dual damascene technique. In general, the “dual damascene technique” may refer to a method in which a structure is formed by filling a trench with a material and polishing the material to be coplanar with the upper surface of the trench. Such a fill and polish technique is generally undesirable for fabricating an aluminum structure, since polishing aluminum is difficult and produces many fabrication issues. In particular, aluminum tends to oxidize easily and aluminum oxide is typically difficult to remove during a polishing process. In addition, even in an embodiment in which aluminum oxide can be removed during a polishing process, the underlying aluminum material is generally softer than aluminum oxide. Consequently, in such an embodiment, the polishing process tends to create several other fabrication problems, including but not limited to scratches, dishing, and surface roughness. As such, aluminum lines are generally formed using a patterning process. Such a patterning process, however does not allow a cladding layer to be formed along the bottom and sidewalls of a structure. Therefore, forming a reliable device with an aluminum field-inducing line having a cladding layer below a memory cell junction is generally improbable.
Copper, on the other hand, may be feasibly fabricated using a dual damascene process and therefore, may be fabricated with a cladding layer. However, the use of copper creates a variety of fabrication concerns, including safety hazards, reliability issues, and the possibility of rendering fabrication equipment and/or devices unusable. In particular, copper has a high solubility with silicon and therefore, can readily change the properties of silicon and its function within a device. Such a change in properties can cause a device to malfunction, rendering the device unusable or at least having reduced reliability. The infusion of copper with silicon may originate through the diffusion of ions within structures and layers of the device during or subsequent to the fabrication process of the device. In addition or alternatively, copper and silicon infusion may occur through contamination of the fabrication equipment. Consequently, fabrication equipment contaminated with copper may need to be cleaned and purged before any further fabrication may be conducted to prevent occurrences of infusing copper with silicon. Such a clean-up process can be extensive, requiring large amounts of time and money. As such, in some embodiments, it may be desirable to limit the amount of copper used in the fabrication of semiconductor devices.
Accordingly, it may be advantageous to develop an MRAM device with a different field-inducing line configuration than used in conventional devices. In particular, it may be advantageous to develop a field-inducing line configuration having relatively low resistivity and, in some embodiments, a cladding layer included therein. In addition, it may be advantageous to develop a field-inducing line configuration that is substantially absent of copper.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by a magnetic random access memory (MRAM) device having a different field-inducing line configuration than used in conventional devices. In some cases, the field-inducing line may include a first layer with a plurality of dielectrically spaced conductive segments. In addition, the field-inducing line may include a second layer with a conductive portion in contact with at least two of the plurality of the dielectrically spaced conductive segments of the first layer. In some embodiments, the conductive portion of the second layer may span across and in contact with all of the dielectrically spaced conductive segments of the first layer. Alternatively, the conductive portion of the second layer may be one of a plurality of dielectrically spaced conductive portions arranged in contact with the plurality of conductive segments of the first layer. In such an embodiment, the plurality of conductive segments of the first layer and the plurality of conductive portions of the second layer may be, in some cases, alternately arranged within the field-inducing line. In other cases, the plurality of conductive segments of the first layer and the plurality of conductive portions of the second layer may be arranged in a different manner.
In any embodiment, the second layer may be arranged vertically closer to magnetic junctions o
Daffer Kevin L.
Lettang Mollie E.
Nelms David
Nguyen Dao H.
Silicon Magnetic Systems
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