Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-07-11
2006-07-11
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S638000, C438S654000, C438S687000
Reexamination Certificate
active
07074709
ABSTRACT:
Methods and compositions are disclosed for modifying a semiconductor interconnect layer to reduce migration problems while minimizing resistance increases induced by the modifications. One method features creating trenches in the interconnect layer and filling these trenches with compositions that are less susceptible to migration problems. The trenches may be filled using traditional vapor deposition methods, or electroplating, or alternately by using electroless plating methods. Ion implantation may also be used as another method in modifying the interconnect layer. The methods and compositions for modifying interconnect layers may also be limited to the via/interconnect interface for improved performance. A thin seed layer may also be placed on the semiconductor substrate prior to applying the interconnect layer. This seed layer may also incorporate similar dopant and alloying materials in the otherwise pure metal.
REFERENCES:
patent: 4955688 (1990-09-01), Chapin et al.
patent: 4995698 (1991-02-01), Myers
patent: 5221060 (1993-06-01), Couvillion et al.
patent: 5594829 (1997-01-01), LoStracco et al.
patent: 5822065 (1998-10-01), Mark et al.
patent: 6023100 (2000-02-01), Tao et al.
patent: 6268291 (2001-07-01), Andricacos et al.
patent: 6376353 (2002-04-01), Zhou et al.
patent: 6387806 (2002-05-01), Wang et al.
patent: 6420262 (2002-07-01), Farrar
patent: 2002/0076925 (2002-06-01), Marieb et al.
patent: 2003/0203617 (2003-10-01), Lane et al.
patent: 2816758 (2002-05-01), None
patent: 2000150522 (2000-05-01), None
patent: WO 0197283 (2001-12-01), None
patent: WO 0245142 (2002-06-01), None
C. P. Wang et al.,Binary Cu-alloy layers for Cu-interconnections reliability improvement(3 pp.).
E. T. Ogawa et al.,Stress-Induced Voiding Under Vias Connected To Wide Cu Metal Leads(10 pp.).
Development of electroless copper metallisation,[online] Retrieved from the Internet:<URL: http://www.hut.fi/Units/Electron/Research/res2000/ElectrolessCu/electroless_copper.html (3 pp.).
Brady III W. James
Brewster William M.
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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