Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-30
2003-10-07
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S295000, C257S900000
Reexamination Certificate
active
06630706
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and, in particular, relates to DRAM devices having improved charge storage capabilities.
2. Description of the Related Art
The Dynamic Random Access Memory (DRAM) device is an important component of electronic systems requiring digital storage capabilities, such as digital computers, personal data assistants (PDA), and the like. The typical DRAM provides an array of memory cells disposed in a high density configuration. For example, a single DRAM device having a minimum feature dimension of 0.15 micron can include an array of millions of directly addressable memory cells that are each capable of storing a single bit of digital data.
FIG. 1
schematically illustrates a typical memory cell
20
comprising a single capacitor
21
and a field effect transistor (FET)
22
. The capacitor
21
stores a quantity of charge which is indicative of the state of the memory cell
20
. The FET
22
acts as a switch that provides a conducting path to the capacitor
21
when the cell
20
is being addressed. The FET
22
also isolates the capacitor
21
when the memory cell
20
is in a quiescent state, i.e., not being addressed, so that the capacitor
20
can store charge for extended periods of time.
As shown in
FIG. 1
, the FET
22
is formed within a substrate
23
and the capacitor
21
formed adjacent the substrate
23
in an interlayer dielectric (ILD) layer
31
. The substrate
23
includes first and second doped regions
24
,
25
and a channel
26
extending therebetween. For example, the first doped
24
region can be configured to be a source input of the FET
22
and the second doped region
25
can be configured to be a drain input of the FET
22
. The FET
22
further comprises a gate electrode
27
disposed over the channel
26
which extends between the source
24
and drain
25
of the FET
22
and is insulated from the substrate
23
by a thin insulating layer
28
. Furthermore, the capacitor
21
comprises first and second plates
29
,
30
separated by an insulating layer
31
, wherein the first plate
29
is coupled to the source of the FET
22
and the second plate
30
is coupled to a fixed reference voltage.
As is well known in the art, when the voltage applied at the gate
27
is greater than a threshold value, the channel
26
becomes a conducting path that allows charge to readily flow between the source
24
and drain
25
. Thus, in response to a write signal arriving at the drain via a digit line
32
, charge is able to flow through the channel
26
to the first plate
29
of the capacitor
21
, thereby providing the capacitor
21
with a quantity of charge which is indicative of the input write signal. Likewise, during a read cycle, an output read signal can be developed at the drain
25
of the FET
22
which is indicative of the charge stored in the capacitor
21
. Furthermore, during quiescent periods when the memory cell
20
is not being addressed, the gate voltage is reduced below the threshold value so as to inhibit conduction across the channel
26
and, thereby, help preserve the charge of the capacitor
21
.
A common problem with memory cells of the prior art is that the capacitor is unable to store charge indefinitely. For example, even if the gate voltage is maintained below the threshold value, a subthreshold leakage current usually flows through the channel
26
which discharges the capacitor during the quiescent period. To accommodate such discharging, typical DRAM devices also include refresh circuitry which periodically monitors the state of each memory cell and repeatedly recharges individual capacitors having a detected residual charge. However, because the DRAM is inaccessible during the refresh cycle, such refreshing reduces the rate at which data can be read from or written to the device. Thus, there is a need to reduce the subthreshold leakage currents so as to extend the time between refresh cycles and, therefore increase the throughput of the device.
One method that can be used to reduce subthreshold leakage currents involves disposing complementary dopant atoms in the channel region of each FET of the memory array. For example, if the source and drain of the FET include pentavalent dopant atoms, such as Phosphorous, the complementary dopant atoms would comprise trivalent dopant atoms, such as Boron. The presence of the complementary dopant atoms within each channel region increases the corresponding threshold gate voltage and, as a result, also increases the resistance of the channel region during quiescent periods.
To ensure that each FET of the memory array is configured with substantially uniform operating characteristics, i.e. uniform gate threshold values, it is important for each channel region to be doped in a substantially identical manner. For example, a first channel region having complementary dopant atoms disposed throughout the first channel region will provide a substantially different gate threshold value than that of a second channel region having a reduced concentration of complementary dopant atoms near its edges. Thus, because of the difficulty of precisely embedding complementary dopant atoms only within the relatively narrow confines of the channel of the typical memory array using conventional masking techniques, the industry has adopted the practice of doping the complementary atoms using a blanket implant process. In other words, no attempt is made to prevent some of the complementary atoms from becoming implanted within regions of the substrate immediately adjacent the channel regions.
The blanket implant process of the prior art comprises exposing a relatively large portion of the substrate corresponding to the entire memory array to a source of energetic complimentary dopant atoms. As a result, complementary dopant atoms
33
are embedded not only within the channel
26
but also in the doped source and drain regions
24
,
25
that surround the channel
26
as shown in
FIG. 1
such that the concentration of complementary dopant atoms is substantially uniform across the source
24
, channel
26
and drain
25
. Unfortunately, the increased concentration of complementary dopant atoms
33
in the source region
24
effectively forms a diode junction with adjacent regions of the substrate
23
. Consequently, the blanket implant process of the prior art produces a relatively large junction leakage current that flows from the source
24
directly into the surrounding substrate
23
. Thus, the reduction in the subthreshold leakage current is gained at the expense of the increase in the junction leakage current which is undesirable since it contributes to the discharging of the capacitor
21
.
From the foregoing, therefore, it will be appreciated that there is a need for a memory array having reduced discharge rates and methods for providing the same. In particular, to provide reduced subthreshold leakage currents, there is a need for the channel regions of the substrate corresponding to the array of memory cells to include complementary dopant atoms disposed so as to increase the threshold gate voltage. Furthermore, to reduce junction leakage currents, there is a need for the complementary dopant atoms to be substantially absent from actively doped regions of the substrate that are coupled to the charge storing capacitors. Finally, there is a need for the complementary dopant atoms to be disposed in such a way that the channel regions of the memory arrays becomes conductive at substantially uniform threshold voltages.
SUMMARY OF THE INVENTION
The aforementioned needs are satisfied by the memory array and method of manufacturing the same of the present invention. In one aspect, the present invention comprises a memory array of a DRAM device that comprises a plurality of memory cells for storing information, wherein the memory cells are arranged into a plurality of cell pairs such that each pair includes first and second cells each comprising a storage element for storing charge and a valve element for contro
Rhodes Howard
Yang Rongsheng
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
Nelms David
Nguyen Dao H.
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