Local skew detecting circuit for semiconductor memory apparatus

Details Local skew detecting circuit for semiconductor memory apparatus Local skew detecting circuit for semiconductor memory apparatus

2011-03-08

2011-03-08

Stoynov, Stefan (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S401000, C326S093000, C327S161000, C327S162000, C365S063000, C365S076000, C711S100000, C716S030000

Reexamination Certificate

active

07904742

ABSTRACT:
A local skew detecting circuit for a semiconductor integrated circuit includes a reference delay block that receives a test signal and generates a reference delay signal by delaying the test signal by a predetermined delay time, and a first timing detecting block coupled with the reference delay block, the first timing detecting block configured to receive the test signal, generate a first delay signal by delaying the test signal by the same predetermined delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.

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