Static information storage and retrieval – Read/write circuit – Particular read circuit
Reexamination Certificate
2009-07-08
2011-11-22
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Read/write circuit
Particular read circuit
C365S228000
Reexamination Certificate
active
08064275
ABSTRACT:
An integrated circuit having an SRAM array includes SRAM cells arranged in rows and columns, and a global read circuit connected to globally read SRAM cells corresponding to accessed rows and columns of the SRAM array. The SRAM array also includes a separate, local sense and feedback circuit connected to a local column of the SRAM array, wherein a sensing portion indicates a memory state of an SRAM cell in an accessed row of the local column and a feedback portion rewrites the memory state back into the SRAM cell. Additionally, a method of operating an integrated circuit having an SRAM array includes providing an SRAM cell in an addressed condition of the SRAM array. The method also includes locally sensing a current memory state of the SRAM cell and locally feeding back to the SRAM cell to retain the memory state during the addressed condition.
REFERENCES:
patent: 6442060 (2002-08-01), Leung et al.
patent: 2004/0085841 (2004-05-01), Lim et al.
Houston Theodore W.
Mair Hugh T.
Brady III Wade J.
Ho Hoai V
Keagy Rose Alyssa
Radke Jay
Telecky , Jr. Frederick J.
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