Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1999-06-30
2002-02-12
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S022000, C710S120000
Reexamination Certificate
active
06347346
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to reconfigurable logic chips. Reconfigurable logic chips, such as field programmable gate arrays (FPGAs) have become increasingly popular. Such chips allow logic to implement different circuits at different times.
FPGAs are also being increasingly used because they offer greater flexibility and shorter development cycles than traditional Application Specific Integrated Circuits (ASICs), while providing most of the performance advantages of a dedicated hardware solution.
One growing popular use of FPGAs is referred to as reconfigurable computing. In reconfigurable computing, hardware logic functions are loaded into the FPGA as needed to implement different sections of a computationally intensive code. By using the FPGAs to do the computational intensive code, advantages are obtained over dedicated processors. Reconfigurable computing is being pursued by university researchers as well as FPGA companies.
A problem with typical FPGAs concerns memory access. One common FPGA memory layout uses a central memory. Unfortunately, accesses to this central memory can form a bottleneck. A large number of access lines are required and, even then, only a certain level of concurrent access is supported.
Other systems create memory units from reconfigurable logic. A disadvantage of these systems is that a large amount of chip “real estate” is required for the reconfigurable logic to implement a memory system. Additionally, programming the reconfigurable logic to implement the memory can be quite complicated.
It is desired to have an improved memory system for a reconfigurable chip.
SUMMARY
The present invention uses dedicated local memory units distributed throughout the reconfigurable logic. The local memory units have system bus ports which allow for quick and easy access with an external system memory. The system bus ports are in addition to local bus ports of the local memory units. The system bus ports allow for system memory transfers done by a direct memory access (DMA) controller on the reconfigurable chip.
In one embodiment, data path units on the reconfigurable chip can initiate the transfer of memory between the system memory and the local memory units. Data path units are reconfigurable elements that execute a number of functions. The initiation of the block data transfer can be the result of a data path unit instruction. The data path units can calculate when to transfer data between the system memory and the local memory units, for example, upon an overflow or underflow of a local memory unit.
In an alternate embodiment, the data path units and local memory units are associated with circuitry to do an automatic cache-like transfer of data between the local memory units and the system memory. This transfer can greatly simplify the programming of the reconfigurable chips. With the cache-like transfer of data, the programming of the reconfigurable chips can substantially ignore the small size of the local memory units. Portions of the system memory can be automatically loaded in and out of the local memory units without requiring programmed steps. This cache-like system is aided by the use of the system memory ports on the local memory units.
Another embodiment of the present invention involves implementing a memory structure using the reconfigurable chip. The implemented memory structure uses local memory units on the reconfigurable chip along with an external memory. During the operation of the memory structure, data is swapped between the local memory unit and the system memory. This swapping is made easier by the use of the system memory port on the local memory units. The implemented memory structure can be made quite large, and is not limited by the size of the local memory units on the reconfigurable chip. The swapping of data in and out of local memory units can occur concurrently with the operation of other local memory units in the implemented memory structure. In the preferred embodiment, data path units can calculate when to swap out or swap in data to and from the local memory units.
One example of an implemented memory structure is a First-In-First-Out (FIFO) buffer. The FIFO buffer is implemented using local memory units acting as a head and tail of the FIFO buffer. The middle of the implemented FIFO buffer can be stored in the system memory.
REFERENCES:
patent: 4122531 (1978-10-01), Tamaru et al.
patent: 4507730 (1985-03-01), Johnson et al.
patent: 4823286 (1989-04-01), Lumelsky et al.
patent: 5025421 (1991-06-01), Cho
patent: 5210749 (1993-05-01), Firoozmand
patent: 5261077 (1993-11-01), Duval et al.
patent: 5295098 (1994-03-01), Kohno
patent: 5298805 (1994-03-01), Garverick et al.
patent: 5392292 (1995-02-01), Davis et al.
patent: 5422856 (1995-06-01), Sasaki et al.
patent: 5560030 (1996-09-01), Guttag et al.
patent: 5692147 (1997-11-01), Larsen et al.
patent: 5703826 (1997-12-01), Hush et al.
patent: 5760607 (1998-06-01), Leeds, et al.
patent: 5793992 (1998-08-01), Steele et al.
patent: 5802554 (1998-09-01), Caceres et al.
patent: 5822618 (1998-10-01), Ecclesine
patent: 5835927 (1998-11-01), Fandrich et al.
patent: 5949719 (1999-09-01), Clinton et al.
patent: 6011407 (2000-01-01), New
patent: 6023421 (2000-02-01), Clinton et al.
patent: 6034538 (2000-03-01), Abramovici
patent: 6038192 (2000-03-01), Clinton et al.
patent: 6044416 (2000-03-01), Hasan
patent: 6049487 (2000-04-01), Plants et al.
patent: 6058063 (2000-05-01), Jang
patent: 6075745 (2000-06-01), Gould et al.
patent: 6088795 (2000-07-01), Vorbach et al.
patent: 6118707 (2000-09-01), Gould et al.
patent: 6130854 (2000-10-01), Gould et al.
Burns Doane , Swecker, Mathis LLP
Chameleon Systems, Inc.
Du Thuan
Lee Thomas
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