Local interconnect using the electrode of a ferroelectric

Details Local interconnect using the electrode of a ferroelectric Local interconnect using the electrode of a ferroelectric

2003-01-07

2004-05-04

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S301000, C257S303000, C257S311000, C257S532000, C257S535000

Reexamination Certificate

active

06730950

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to semiconductor memory devices and more particularly to memory structures and methods for forming a local interconnect layer within a conductive plate of a ferroelectric capacitor in a ferroelectric memory device.
BACKGROUND OF THE INVENTION
In semiconductor memory devices, data is read from or written to the memory using address signals and various other control signals. In a random access memory (“RAM”), an individual binary data state (e.g., a bit) is stored in a volatile memory cell, wherein a number of such cells are grouped together into arrays of columns and rows accessible in random fashion along bitlines and wordlines, respectively, wherein each cell is associated with a unique wordline and bitline pair. Address decoder control circuits identify one or more cells to be accessed in a particular memory operation for reading or writing, wherein the memory cells are typically accessed in groups of bytes or words (e.g., generally a multiple of 8 cells arranged along a common wordline). Thus, by specifying an address, a RAM is able to access a single byte or word in an array of many cells, so as to read or write data from or into that addressed memory cell group.
Two major classes of random access memories include “dynamic” (e.g., DRAMs) and “static” (e.g., SRAMs) devices. For a DRAM device, data is stored in a capacitor, where an access transistor gated by a wordline selectively couples the capacitor to a bit line. DRAMs are relatively simple, and typically occupy less area than SRAMs. However, DRAMs require periodic refreshing of the stored data, because the charge stored in the cell capacitors tends to dissipate. Accordingly DRAMs need to be refreshed periodically in order to preserve the content of the memory. SRAM devices, on the other hand, do not need to be refreshed. SRAM cells typically include several transistors configured as a flip-flop having two stable states, representative of two binary data states. Since the SRAM cells include several transistors, however, SRAM cells occupy more area than do DRAM cells. However, SRAM cells operate relatively quickly and do not require refreshing and the associated logic circuitry for refresh operations.
A major disadvantage of SRAM and DRAM devices is volatility, wherein removing power from such devices causes the data stored therein to be lost. For instance, the charge stored in DRAM cell capacitors dissipates after power has been removed, and the voltage used to preserve the flip-flop data states in SRAM cells drops to zero, by which the flip-flop loses its data. Accordingly, SRAMs and DRAMs are commonly referred to as “volatile” memory devices. Non-volatile (NV) memories are available, such as Flash and EEPROM. However, these types of non-volatile memory have operational limitations on the number of write cycles. For instance, Flash memory devices generally have life spans from 100K to 10MEG write operations.
Recently however, non-volatile ferroelectric RAM devices have been developed, which are commonly referred to as FERAMs or FRAMs. FERAM cells employ ferroelectric capacitors (FECaps) including a pair of capacitor plates with a ferroelectric material, such as SBT or PZT, as the capacitor dielectric situated between them. Ferroelectric materials have two different stable polarization states that may be used to store binary information, where the ferroelectric behavior follows a hysteresis curve of polarization versus applied voltage. FERAM memory cells are non-volatile memory devices, because the polarization state of an FECap remains when power is removed from the device.
Two types of memory cells are used commonly, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1T/1C or 1C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise, process and cycling variations. Additionally, a 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2C memory cell generally is more stable than a 1C memory cell.
As illustrated in prior art
FIG. 1
, a 1T/1C FeRAM cell
10
includes one transistor
12
and one ferroelectric storage capacitor
14
. A bottom electrode of the storage capacitor
14
is connected to a drain terminal
15
of the transistor
12
. The 1T/1C cell
10
is read from by applying a signal to the gate
16
of the transistor (word line WL)(e.g., the Y signal), thereby connecting the bottom electrode of the capacitor
14
to the source of the transistor (the bit line BL)
18
. A pulse signal is then applied to the top electrode contact (the drive line DL or plate line PL)
19
. The potential on the bit line
18
of the transistor
12
is, therefore, the capacitor charge divided by the bit line capacitance. Since the capacitor charge is dependent upon the bi-stable polarization state of the ferroelectric material, the bit line potential can have two distinct values. A sense amplifier (not shown) is connected to the bit line
18
and detects the voltage associated with a logic value of either 1 or 0. Frequently, the sense amplifier reference voltage is provided by a “reference cell”, which comprises a ferroelectric or non-ferroelectric capacitor connected to another bit line that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of the shown ferroelectric memory cell is that a read operation is destructive. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. Since the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. One difference from a DRAM is that a ferroelectric memory cell will retain its state until it is interrogated, thereby eliminating the need of refresh.
As illustrated, for example, in prior art
FIG. 2
, a 2T/2C memory cell
20
in a memory array couples to a bit line
22
and an inverse of the bit line (“bit line-bar”)
24
that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors
26
and
28
and two ferroelectric capacitors
30
and
32
, respectively. The first transistor
26
couples between the bit line
22
and a first capacitor
30
, and the second transistor
28
couples between the bit line-bar
24
and the second capacitor
32
. The first and second capacitors
30
and
32
have a common terminal or plate line PL
34
to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors
26
and
28
of the dual capacitor ferroelectric memory cell
20
are enabled (e.g., via their respective word line WL
36
) to couple the capacitors
30
and
32
to the complementary logic levels on the bit line
22
and the bar-bar line
24
corresponding to a logic state to be stored in memory. The common terminal
34
of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell
20
to one of the two logic states.
In a read operation, the first and second transistors
26
and
28
of the dual capacitor memory cell
20
are enabled via the word line
36
to couple the information stored on the first and second capacitors
30
and
32
to the bit line
22
and the bit line-bar line
24
, respectively. A differential signal (not shown) is thus generated across the bit line
22
and the bit line-bar line
24
by the dual capacitor memory cell
20
. The differential signal is sensed by a sense amplifier (not shown) that provides a signal corresponding to the lo

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