Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2007-08-21
2007-08-21
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S597000, C257SE21507, C257SE21582, C257SE21590
Reexamination Certificate
active
10971961
ABSTRACT:
The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a protective layer. The second cavity is then formed adjacent to the first cavity and extends down to expose the underlying etch stop layer. The protective layer is removed to form an expanded cavity including the first and second cavities which expose the underlying etch stop layer in the expanded cavity. The etch stop material in the expanded cavity is also removed to expose an underlying gate contact and expose one of a source or drain contact. The gate contact is then electrically connected with one of the exposed source or drain contacts to form a local interconnect.
REFERENCES:
patent: 4997790 (1991-03-01), Woo et al.
patent: 5902132 (1999-05-01), Mitsuhashi
patent: 6093629 (2000-07-01), Chen
patent: 6197639 (2001-03-01), Lee et al.
patent: 6207543 (2001-03-01), Harvey et al.
patent: 6383878 (2002-05-01), Huang
patent: 6413827 (2002-07-01), Farrar
patent: 6420273 (2002-07-01), Lin
patent: 6548394 (2003-04-01), Peng et al.
patent: 6781192 (2004-08-01), Farrar
patent: 6784552 (2004-08-01), Nulty et al.
patent: 6803318 (2004-10-01), Qiao et al.
patent: 2002/0146897 (2002-10-01), Nulty et al.
patent: 2003/0082900 (2003-05-01), Peng et al.
patent: 2003/0113973 (2003-06-01), Chu
Bhatt Hemanshu D.
Menon Santosh S.
Pritchard David
Beyer Weaver LLC
Geyer Scott B.
Isaac Stanetta
LSI Corporation
LandOfFree
Local interconnect manufacturing process does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Local interconnect manufacturing process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Local interconnect manufacturing process will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3899369