Local interconnect formed using silicon spacer

Details Local interconnect formed using silicon spacer Local interconnect formed using silicon spacer

2000-06-06

2004-03-09

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S754000, C257S768000

Reexamination Certificate

active

06703668

ABSTRACT:

TECHNICAL FIELD
The present claimed invention relates to the field of semiconductor devices. More specifically, the present claimed invention relates to a local interconnect for a semiconductor device.
BACKGROUND ART
As the demand for high performance, high density integrated circuit devices increases, the ability to offer ever smaller Static Random Access Memory (SRAM) cells becomes critical. As the device feature size shrinks, the SRAM cell size becomes interconnect limited. One way to minimize the cell size is to use local interconnects (instead of metal
1
and contacts) to strap gates and diffusion areas.
In one recent prior art method for forming local interconnects, dielectric spacers are formed on each side of each gate. A portion of an dielectric spacer is removed using mask and etch steps so as to form a exposed region on the side of the gate. Self-aligned silicidation (SALICIDE) is used to form an interconnect structure that electrically connects the gate to the diffusion area.
Prior art
FIG. 1A
shows a diagram of a local interconnect formed according to a prior art process. Silicide region
3
extends over the top of polysilicon gate
2
and silicide region
4
extends over silicon substrate
1
such that it at least partially overlies diffusion region
5
. However, the sidewall of the polysilicon gate
2
does not form a continuous layer of silicide. The poor sidewall silicidation is primarily due to metal thinning associated with sputtering shadowing and to residual surface oxide left over from prior processing steps (polysilicon reoxidation, spacer removal, etc.). Thus, the gate-to-diffusion connection relies on the silicide at the bottom corner
10
where the sidewall of polysilicon gate
2
meets silicide region
4
. The resulting electrical connection is unreliable as it relies on electrical connection via the tip of silicide region
4
at bottom corner
10
and relies on conductivity through polysilicon gate
2
.
In structures that use Shallow Trench Isolation (STI) for isolating diffusion areas, dielectric material is disposed in shallow trenches. When the polysilicon gate does not overlie the diffusion area, disconnection results. Prior art
FIG. 1B
shows a disconnection
20
that results from the placement of polysilicon gate
2
over STI dielectric
21
. Disconnection problems of this type typically result from photolithography misalignment.
Another problem with prior art local interconnects is junction leakage. Junction leakage typically occurs as a result of rough silicide formation because the diffusion junction is abruptly delineated along the gate edge, creating a junction punch-through (a conductive path into the semiconductor substrate). This is in contrast to the normal situation where the source/drain extension along a spacer edge provides extra protection against silicidation induced junction leakage.
FIG. 1C
shows junction punch-through
30
that is a conductive path resulting from rough silicide formation during the formation of silicide region
4
.
Thus, a need exists for a local interconnect and a method for forming a local interconnect that produces a local interconnect that is robust and that makes good electrical connection. Also, a local interconnect and a method for making a local interconnect is required that meets the above need and that does not have silicidation induced junction leakage. The present invention provides a solution to the above needs.
DISCLOSURE OF THE INVENTION
The present invention provides a local interconnect structure that includes a silicon spacer. The local interconnect of the present invention is more robust than prior art interconnect structures.
First, gates and spacers are formed on a silicon substrate using conventional fabrication processes. In one embodiment, polysilicon is deposited, masked and etched to form gates. Spacers are then formed by the deposition of a dielectric layer that is etched to form spacers on opposite sides of each gate.
A portion of a spacer is removed so as to form an open region (exposing a portion of the sidewall of the spacer) where local interconnection is to be formed. A thin screen oxide is deposited over the wafer, followed by formation of a diffusion region. In one embodiment, implantation and rapid-thermal annealing are used to form a diffusion region that includes source/drain structures. A layer of silicon (either amorphous or polycrystalline) is then deposited, followed by selective silicon etching to form a silicon spacer along the open region.
A conventional self-aligned silicidation (SALICIDE) process is performed, leading to simultaneous silicidation on diffusion, gate, and along the silicon spacer, forming a local interconnect between the gate and the diffusion.
The local interconnects of the present invention are more robust and reliable than prior art local interconnects. This is primarily due to the fact that the metal thickness, hence silicide thickness, along the silicon spacer is close to that on the gate and on the diffusion region. More particularly, because the silicide surface in the present invention is raised above the original silicon surface, the outward expansion of silicide will result in a continuous silicide layer formation at the local interconnect. Second, since the metal thickness around the intersection between the silicon spacer and the diffusion region is significantly thicker (approximately 300 Angstroms) than the oxide, there is plenty of metal supply for silicide formation, thus enhancing the formation of a continuous silicide at those interface points. This results in silicide that is reliable at the joint points between the silicon spacer and the diffusion region and between the silicon spacer and the gate.
In structures that use Shallow Trench Isolation (STI) for isolating diffusion areas, a good electrical connection results even when the gate does not overlie the diffusion area. Thus, the local interconnect and method for forming a local interconnect of the present invention does not result in disconnection, as typically occurs in prior art processes from photolithography misalignment.
Silicidation on the silicon substrate occurs over source/drain regions where the junction is relatively deep. Therefore, rough silicide formation does not result in junction punch-through as occurs in prior art processes. Thus, the local interconnect structure and method of the present invention does not produce junction leakage as occurs in prior art methods.
Thus, the present invention provides a local interconnect structure and a method for forming a local interconnect structure that produces a local interconnect that is robust and that makes good electrical connection. Also the local interconnect structure and the method for making a local interconnect structure of the present invention does not have silicidation induced junction leakage.


REFERENCES:
patent: 5290720 (1994-03-01), Chen
patent: 5483104 (1996-01-01), Godinho et al.
patent: 5614747 (1997-03-01), Ahn et al.
patent: 6255701 (2001-07-01), Shimada

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