Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-28
2003-06-10
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000
Reexamination Certificate
active
06576544
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to the field of integrated circuit manufacturing. More particularly, this invention relates to an improved method for constructing an integrated circuit whereby the routing density of electrically conductive interconnects on any particular interconnect layer is generally increased, and the overall number of interconnect layers required for a particular integrated circuit is generally decreased.
BACKGROUND
Integrated circuits are typically formed of layers of electrically semiconducting materials, electrically insulating materials, and electrically conducting materials that are layered in a complex series of processes such as doping, deposition, and etching of the materials in progressive layers. Typically, the various circuit elements within the integrated circuit are electrically connected using layers of the electrically conductive material, such as metal. These layers of electrically conductive material are usually patterned into interconnects. Several layers of interconnects may be used in the fabrication of a completed integrated circuit. Typically, each level of interconnects in an integrated circuit runs primarily in either the X or Y direction to allow for the electrical connection of the transistors and the macro elements that form an integrated circuit.
Sometimes it is desirable for two or more elements disposed on an X direction interconnect level, for example, to be electrically connected in a Y direction. In this manner, an electrical connection can be made between two or more elements that are in close proximity to one another, without requiring the connection to be made on a different level of electrical interconnects, which may reduce the total number of interconnect layers. However, when such a transverse electrical connection is made, it typically requires that no other electrical connections can be made in the area of the transverse electrical connection. In other words, it is typically preferred that none of the electrical interconnections within a single layer cross, or the electrical interconnections create a mass of short circuited connections. Thus, the use of a short transverse electrical connection tends to reduce the density of the electrical interconnect layer in which it is used.
The macro elements within an integrated circuit, such as resistors, fuses, and capacitors, are also constructed utilizing electrically conductive materials and other materials. However, the electrical properties of the conductive materials used for the macro elements are somewhat different from the electrical properties of the conductive materials used for the electrical interconnect layers. For example, the bulk resistance of the electrically conductive material used to form the macro elements is often much greater than that which is desirable for use in the electrical interconnect layers. One reason for this is that many of the macro elements are designed to be resistive elements or are otherwise not designed to carry an appreciable amount current for any significant distance. However, the electrical interconnect layers, on the other hand, are primarily designed to carry an appreciable amount of current for a significant distance, and preferably without a significant voltage drop. Therefore, the desired electrical properties of the different electrically conductive materials used for the macro elements and the electrical interconnect layers tend to be mutually exclusive.
Therefore, what is needed is an improved method of manufacturing integrated circuits that generally increases the routing density of the interconnect layers and generally decreases the overall number of interconnect layers.
SUMMARY
The above and other needs are met by a method for forming an electrically conductive local interconnection between circuit elements of an integrated circuit. A first layer of conductive material is deposited on a substrate. This conductive material has a relatively low bulk electrical resistance. A pattern is etched out of the first layer of conductive material to form a first conductive circuit layer having first conductive elements on the substrate. A first layer of insulating material, preferably a silicon oxide such as silicon dioxide, is deposited on top of the first conductive circuit layer.
In an alternate embodiment, the first insulating layer is a layer of high density plasma oxide that is deposited such that the layer of high density plasma oxide fills in gaps between the first conductive circuit elements. After deposition, the first layer of insulating material is patterned to form local interconnection points on a least two of the first conductive elements such that the local interconnection points are within a predetermined distance of each other. A second layer of conductive material is deposited over the patterned first layer of insulating material. This second layer of conductive material has a relatively high bulk resistance as compared to the first layer of conductive material.
The second layer of conductive material is preferably a layer of titanium nitride that is between about one hundred angstroms and about five thousand angstroms in thickness. This second layer of conductive material is patterned to form the electrically conductive local interconnection between the at least two of the first conductive elements. The second layer of conductive material is also used to form portions of macro circuit elements that are designed to function with the relatively high bulk electrical resistance of the second layer of conductive material. These macro circuit elements may include circuit elements such as capacitor electrodes, resistors and fuses.
A second insulating layer is deposited over the second layer of conductive material, and preferably planarized. Vias are etched in the second layer of insulating material to provide electrical connection points to the electrically conductive local interconnections and the first conductive elements. Finally, a third layer of conductive material having a relatively low bulk resistance is deposited over the second insulating layer and patterned such that the vias provide electrical interconnections between the patterned first layer of conductive material, the second layer of conductive material and the patterned third layer of conductive material.
The present invention tends to decrease the complexity and increase the routing density of the interconnect levels by removing some of the interconnect lines from the interconnect levels through the use of relatively short conductive local interconnections constructed from a conductive material that has a resistance that is higher than the conductive material typically used to form the interconnect levels. The material used to form the local electrical interconnections is the same material used to form macro circuit elements such as resistors, capacitor electrodes, and fuses and is applied during the same manufacturing process used to form these macro circuit elements. By producing these local conductive interconnects during the same manufacturing step used to produce the macro circuit elements, the method of the present invention tends to reduce the total number of steps required to produce an integrated circuit. Thus, the present invention tends to reduce the cost of constructing an integrated circuit.
In another embodiment, the present invention is directed toward a method of forming an electrically conductive local interconnect on an integrated circuit. A first layer of conductive material is deposited on a substrate, where the first layer of conductive material has a relatively low bulk electrical resistance. The first layer of conductive material is patterned to form a first conductive circuit layer on the substrate, where the first conductive circuit layer has first conductive elements. A first layer of insulating material is deposited on top of the first conductive circuit layer.
A second layer of conductive material is deposited over the first layer of insulating material, where the second layer of conductive material
Allman Derryl D. J.
Hightower James R.
Saopraseuth Phonesavanh
Chaudhuri Olik
Kebede Brook
LSI Logic Corporation
Luedeka Neely & Graham
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