Local ground and VCC connection in an SRAM cell

Details Local ground and VCC connection in an SRAM cell Local ground and VCC connection in an SRAM cell

2005-07-12

2005-07-12

Saadat, Mahshid D. (Department: 2503)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000, C257S371000, C257S903000

Reexamination Certificate

active

06917083

ABSTRACT:
A retrograde well region, having a buried layer of high conductivity, is formed in a semiconductor substrate. A trench structure is selectively etched in the semiconductor substrate down to a region proximate to or within the buried layer. A conducting local interconnect material is formed within and proximate to the trench structure to electrically connect surface portions of the substrate to the buried layer. The buried layer is used to provide a voltage source to an integrated circuit. In one application, a P-type buried layer provides ground potential or VSSto a source region of an N-channel FET transistor. In a second application, an N-type buried layer provides supply potential or VCCto a source of a P-channel FET transistor.

REFERENCES:
patent: 4689871 (1987-09-01), Malhi
patent: 4933739 (1990-06-01), Harari
patent: 5378914 (1995-01-01), Ohzu et al.
Wolf, S.; Tauber, R.N.Silicon Processing for the VLSI Era,Lattice Press, Sunset Beach, CA, 1986 pp. 280-281.

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