Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2002-02-23
2004-02-17
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S797000, C438S401000, C438S462000, C438S745000
Reexamination Certificate
active
06693365
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to exposing alignment mark regions of semiconductor wafers after the wafers having been electrochemically metal plated, and more particularly to such exposure via local electrochemical deplating of the alignment mark regions.
BACKGROUND OF THE INVENTION
Alignment is critical in photolithography and deposition, as well as in other semiconductor processes. If layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, relegating them to scrap, which can be costly. Therefore, alignment marks are placed on the semiconductor wafer for the proper positioning during the deposition and photolithography processes, among other processes. This is shown in
FIG. 1
, where the semiconductor wafer
102
has alignment marks
102
and
104
thereon. The semiconductor wafer
102
also has a number of dies, such as the die
108
. Thus, when a mask is positioned over the wafer
202
, its own alignment marks are aligned with the alignment marks
102
and
104
of the wafer
202
.
As one example, alignment is especially critical where a number of metal or other layers have already been deposited on the wafer. Subsequent deposition of silicon dioxide or other layers in such instances usually requires that the alignment marks on the wafer be exposed for proper overlay of the silicon dioxide or other layers. While a mask may prevent the layers themselves from obfuscating the alignment marks, the photoresist used to pattern or perform other processing of these layers cannot be masked, and covers or at least blurs the alignment marks. Without clear exposure of the alignment marks, however, overlay misalignment can result. Overlay misalignment is also referred to as overlay registration error. Misalignment is a serious problem, and can result in significant semiconductor wafer scrap. Wafer scrap can sometimes be reused, but often is discarded, resulting in added costs incurred by the semiconductor foundry.
In some semiconductor fabrication processes, such as the copper damascene process known within the art, the semiconductor wafer is electrochemically plated with a metal, such as copper, tantalum nitride, both copper and tantalum nitride, and so on. This is shown in FIG.
2
. The wafer
102
of
FIG. 1
is indicated as the wafer
102
′, because it has been electrochemically metal plated, as indicated by the shading over its entire surface. The alignment marks
104
and
106
are obfuscated by the electrochemical metal plating, and should be exposed before further semiconductor fabrication processes that require alignment are performed on the wafer
102
′.
Conventional alignment mark exposure processes, however, can also ruin a number of dies on the semiconductor wafer.
FIG. 3
shows the results of exposing alignment marks after electrochemical metal plating, and optionally chemical mechanical polishing (CMP). The wafer
102
′ of
FIG. 2
is indicated as the wafer
102
″ after exposure of the alignment marks. The alignment marks
104
and
106
are exposed by using an edge or bevel cleaner that removes the electrochemically plated metal from the wafer on a circular band
302
around the edge of the semiconductor wafer
102
″. Therefore, the semiconductor wafer
102
″ remains electrochemically plated everywhere on its surface except on the band
302
.
As can be seen in
FIG. 3
, however, the exposure of alignment marks
104
and
106
by using an edge or bevel cleaner after electrochemical metal plating can also disadvantageously remove the electrochemical metal plating from some of the dies of the wafer
102
″, such as the die
108
. These dies are shown in
FIG. 3
as being only partially shaded, and thus being only partially covered by electrochemical metal plating. The edge or bevel cleaning process, in other words, while exposing the alignment marks
104
and
106
, also undesirably removes some of the electrochemical metal plating of some of the dies, such as the die
108
. This is disadvantageous, because it decreases die yield. The dies that have had some of their electrochemical metal plating removed are no longer usable, and must be discarded.
Therefore, there is a need to expose alignment marks after electrochemical metal plating that avoids these drawbacks. Specifically, there is a need to expose the alignment marks on a semiconductor wafer that has been electrochemically metal plated without affecting die yield. That is, there is a need to remove the electrochemical metal plating from the alignment marks, without also removing the electrochemical metal plating from one or more of the dies of the wafer. For these and other reasons, there is a need for the present invention.
SUMMARY OF THE INVENTION
The invention relates to local electrochemical deplating of alignment mark regions of semiconductor wafers. A tank holds an electrolytic solution. A primary cathode submersed within the solution is at least partially insulated therefrom. A semiconductor wafer submersed within the solution acts as an anode, and has one or more alignment mark regions. The semiconductor wafer has been electrochemically metal plated. Extension cathodes submersed within the electrolytic solution are each at least partially insulated, except for a part of a first end and a second end thereof. The first end part is closely positioned over a corresponding alignment mark region, whereas the second end is situated on a corresponding exposed part of the primary cathode. A power source has its positive terminal operatively coupled to the primary cathode and its negative terminal operatively coupled to the wafer. Current from the power source electrochemically deplates the metal substantially from the alignment mark regions, substantially exposing the alignment marks within these regions.
Embodiments of the invention provide for advantages over the prior art. The primary cathode and the extension cathodes are at least partially insulated from the electrolytic solution, except where one extension cathode end connects to the primary cathode and where the other extension cathode end is closely positioned over an alignment mark region. Therefore, electrochemical deplating substantially exposes only the alignment mark regions under the exposed ends of the extension cathodes. Little or no electrochemical deplating occurs on other parts of the semiconductor wafer, such as the dies of the wafer. Therefore, die yield does not decrease as a result of the alignment mark exposure process of the invention. Still other aspects, advantages, and embodiments of the invention will become apparent by reading the detailed description that follows, and by referring to the accompanying drawings.
REFERENCES:
patent: 4632724 (1986-12-01), Chesebro et al.
patent: 6056869 (2000-05-01), Uzoh
patent: 2002/0153246 (2002-10-01), Wang
patent: 2002/0155661 (2002-10-01), Massingill et al.
Huang Chen-Ming
Yang Sen-Shan
Hogans David L.
Jr. Carl Whitehead
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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