Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1995-07-05
2001-10-23
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
Reexamination Certificate
active
06308236
ABSTRACT:
TECHNICAL FIELD OF INVENTION
The invention relates to the address decoding scheme and, in particular, to dynamic address decoding scheme of a local bus within a computer system.
BACKGROUND OF THE INVENTION
The introduction of high speed local bus has greatly improved the performance of the peripheral devices as compared to the traditional expansion bus.
As shown in
FIG. 1
, a typical computer system includes multiple hierarchical bus interfaces The one closest to CPU is the CPU bus and the one behind the bridge device is the local bus which runs at high speed with very high transfer rate between the CPU and high speed peripherals, such as graphics, video and disk device. The last one is the expansion bus including well known ISA, EISA or micro-channel bus.
The access to the peripheral devices by the CPU starts as CPU asserts address/data start (ADS) signal and the access is completed successfully as the associated controller asserts a READY signal to the CPU. The performance of the computer system is measured by the speed of which the system responds with the READY signal.
A CPU cycle could be addressed to the devices on any one of the three buses which are organized in a hierarchical architecture. If devices on the CPU bus, e.g. cache or memory, is addressed, CPU bus responds first. To the next level, CPU bus cycles are required to translate the CPU cycle into the local bus cycle. After a predetermined amount of time, if no device on the local bus responds, the cycle will be further passed to the expansion bus. The completion of the expansion bus cycle is indicated by the READY signal generated by the shown system chipset. The latency from the start of ADS signal of CPU to the assertion of READY signal by the associated controller includes time overhead of bus cycle conversion by the bridge device and the time overhead spent on receipt of the acknowledgement from local bus device when no post-write buffers are provided.
It is well known that the bridge device has built-in post-write buffers for speeding up the write cycle operation. The post-write buffers technique employed requires, before hand, the knowledge of addressing range of the peripheral devices under the bus. As such, the buffer manager device then may actively respond to an access request without actually obtaining the assertion of the peripheral devices.
The mechanism of the post-write buffers involves the temporary storage of the data into the buffers and immediate response to the CPU with READY signal thereafter without actual acknowledgement from the local bus device. Accordingly, CPU is allowed to proceed next cycle in concurrence with the local bus cycle completing the operation of the data, stored within the post-write buffer, in connection with the associated local bus device.
In any way, the bridge device should not acknowledge the CPU cycle with the READY signal unless it knows the CPU cycle is addressed to the device on the local bus. Furthermore, if, before hand, the CPU cycle could not be recognized as being addressed to the device on the local bus, the post-write buffers, though provided in the bridge device, are useless. Therefore, the key to use the provided post-write buffers is the before-hand knowledge of the bridge device over the CPU cycle addressing the device on the local bus.
One conventional approach, called static window, is provided for fully taking advantage of the post-write buffers. The system software, e.g. BIOS or OS, must first program the address windows, which is responded by the local bus devices, into the bridge device. The bridge device then decodes the CPU cycle and determines if the address of the cycle falls within any of the windows.
This approach has several inherent disadvantages. First of all, there is no way for system software to know the address ranges of all devices sold in the marketplace and compatibility is a issue. Second, the approach might rely on end-user's knowledge to program new address windows into the bridge device when a new local bus device is first installed. It is quite unacceptable since the general end-user has no such technical background. Third, the number of local bus device to be placed on the local bus is uncertain and varies among different users and it is difficult to know how many address windows will be actually required.
To overcome the deficiency of the conventional approach, it is the main objective of the invention to use the post-write buffers with simplification of BIOS or OS support.
SUMMARY OF THE INVENTION
The invention provided includes a dynamic decoding device, a local bus interface device, a First-In-First-Out data buffer and an acknowledge generator.
The dynamic decoding device is coupled to the CPU address lines and generates a HIT signal when an address value on the CPU address lines of the present CPU cycle falls within a predetermined range of a previous address value of a previous CPU cycle. The previous address value was stored in the register within the dynamic decoding device.
The local bus interface device is coupled to the local bus, and it triggers a local bus cycle on the local bus and generates an acknowledge signal when the address value of the present CPU cycle does not fall within the predetermined range of the previous address value of the previous CPU cycle which is indicated by the inactive status of HIT signal. And, in response to the HIT signal, the local bus interface device generates a plurality of control signals to the local bus.
The First-In-First-Out data buffer is coupled to the CPU data lines and the local bus, and transmits data from the CPU data bus to local bus under the control of the plurality of control signals.
The acknowledgement generator, responsive to the HIT signal, generates a READY signal to the CPU.
REFERENCES:
patent: 5045998 (1991-09-01), Begun et al.
patent: 5325499 (1994-06-01), Kummer et al.
patent: 5333276 (1994-07-01), Solari
Auve Glenn A.
Fish & Richardson P.C.
VIA Technologies Inc.
LandOfFree
Local bus with dynamic decoding capability does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Local bus with dynamic decoding capability, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Local bus with dynamic decoding capability will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2554260