Local bit switch decode circuit and method

Details Local bit switch decode circuit and method Local bit switch decode circuit and method

2000-09-28

2001-12-04

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S063000, C365S207000

Reexamination Certificate

active

06327215

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a global bit switch circuit and method for activating a bit switch across a number of sense amplifier sections in more than one bank of sense amplifiers which avoids disruption of non selected sense amplifiers.
(2) Description of the Related Art
U.S Pat. No. 5,923,605 to Mueller et al. describes a multi-bank DRAM capable of overlapped reading and writing to different banks of the DRAM.
U.S. Pat. No. 5,812,473 to Tsai describes a DRAM having a sense amplifier connected to a bit line pair of a memory cell array through a column select switch. The data line pairs are provided with pass gates. A first pair of gates connects a sense amplifier output of a bit line pair to a first data line pair and a second pair of gates connects the sense amplifier output of the bit line pair to a second data line pair. Each bit line pair can be connected through a sense amplifier to either first or second data line pairs.
U.S. Pat. No. 5,949,732 to Kirihata describes a method for structuring a multi-bank DRAM into a hierarchical column select line architecture. The DRAM has multiple banks with a switch for selecting one of the banks and a switch for selecting one of the columns within the bank. This allows switches to couple one of the bit lines to one of the data lines, enabling data to be written into or read out of memory cells common to the selected bank and to the selected column.
SUMMARY OF THE INVENTION
Many SDRAM, static dynamic random access memory, designs use a number of banks of sense amplifiers having an equal number of sense amplifiers in each bank. These designs usually have two or four banks of sense amplifiers. Pass gates in each of the sense amplifiers provide means to connect data lines to or isolate data lines from the sense amplifiers. Many of these designs use a global bit switch scheme wherein the bit switch will be activated across a number of sense amplifiers within a single bank simultaneously. Multi bank architecture designs allow for more than one bank to be open at a time. In multi bank designs the global bit switch can potentially cause disruption in non selected sense amplifiers and a local bit switch must be used. Chip area is a critical aspect that must be considered in the local bit switch design.
FIG. 1
shows a diagram of a local bit switch selecting circuit using NOR, Not OR, gates as local bit switches. The circuit of
FIG. 1
has a first number, L, of sense amplifier banks
11
(i) each having a second number, M, of sense amplifiers
10
(ij). Each of the sense amplifiers
10
(ij) has a first input connected to a first pass gate
12
(ij) and a second input connected to a second pass gate
13
(ij). Each of the first pass gates
12
(ij) are connected in series between the first input
18
(ij) of one of the sense amplifiers and a first data line
14
(ij). Each of the second pass gates
13
(ij) are connected in series between the second input
19
(ij) of one of the sense amplifiers and a second data line
15
(ij). In the reference numbers
12
(ij),
13
(ij),
14
(ij),
15
(ij),
18
(ij), and
19
(ij), i takes on all integer values from 1 to L and j takes on all integer values from 1 to M. The first pass gates
12
(ij) each consist of a first N channel field effect transistor having a source, drain and gate and the second pass gates
13
(ij) each consist of a second N channel field effect transistor having a source, drain, and gate. The first input
18
(ij) of each of the sense amplifiers is connected to the drain of one of the first N channel field effect transistors
12
(ij) and the source of that first N channel field effect transistor
12
(ij) is connected to the corresponding first data line
14
(ij). The second input
19
(ij) of each of the sense amplifiers is connected to the drain of one of the second N channel field effect transistors
13
(ij) and the source of that second N channel field effect transistor
13
(ij) is connected to the corresponding second data line
15
(ij).
In the above description, and in the descriptions to follow the first number, L, is a positive integer greater than one, typically but not necessarily four, and the second number, M, is a positive integer greater than one. In the reference numbers
10
(ij),
11
(i),
12
(ij),
13
(ij),
14
(ij),
15
(ij),
18
(ij), and
19
(ij), i takes on all integral values from 1 to L and j takes on all integral values from 1 to M.
The circuit shown in
FIG. 1
uses L NOR gates
20
(i) as local bit select switches, one in each of the L sense amplifier banks. Each of the NOR gates has two inputs. A first input of each of the NOR gates is connected to a local bit select line
30
(i). The second inputs of the all of the NOR gates are connected together and to a global bit select line
400
. In the reference numbers
20
(i) and
30
(i), i takes on all integer values from 1 to L.
As can be seen from
FIG. 1
when the global bit line
400
is high none of the pass gates,
12
(ij) and
13
(ij), will be activated. When the global bit line
400
is low the pass gates,
12
(ij) and
13
(ij), in a sense amplifier bank
11
(i) having a low local bit line
30
(i) will be activated; and the pass gates,
12
(ij) and
13
(ij), in a sense amplifier bank
11
(i) having a high local bit line
30
(i) will not be activated.
Another possible local bit switch design is shown in FIG.
2
. In the circuit in
FIG. 2
each of the local bit lines
30
(i) are connected to a circuit comprising an inverter
22
(i) and a pass gate
24
(i). For each of the local bit lines
30
(i), an NMOS transistor
25
(i) is connected between the V
ss
supply and the output node
27
(i) of the pass gate
24
(i). In this NMOS transistor
25
(i) the drain is connected to the pass gate
24
(i) output node
27
(i), the source connected to the V
ss
supply, and the gate connected to the inverter
22
(i) output. The purpose of these NMOS transistors
25
(i) is to keep the output node
27
(i) of the pass gate
24
(i) from floating when the voltage at node
400
is low. In the reference numbers
22
(i),
24
(i),
25
(i),
27
(i), and
30
(i), i takes on all integer values from 1 to L. As can be seen from
FIG. 2
when the global bit line
400
is low the local bit lines
30
(i) are isolated from the pass gates,
12
(ij) and
13
(ij). When the global bit line
400
is high the local bit lines
30
(i) are connected to the pass gates,
12
(ij) and
13
(ij); so that the pass gates,
12
(ij) and
13
(ij), in a sense amplifier
11
(i) having a high local bit line
30
(i) will be activated and the pass gates,
12
(ij) and
13
(ij), in a sense amplifier bank
11
(i) having a low local bit line
30
(i) will not be activated.
A problem with the circuit shown in
FIG. 1
is that each of the NOR gates
20
(i) requires four transistors. The problem with the circuit shown in
FIG. 2
is that each of the inverters
22
(i) requires two transistors, each of the pass gates
24
(i) requires two transistors, and an extra transistor
25
(i) results in a total of five transistors in each of the sense amplifier banks. With a premium on chip area it is desirable to have local bit switches which uses fewer transistors and less chip area.
It is a principle objective of this invention to provide 1 local bit switch design for global bit switch decoding schemes in multi bank sense amplifier arrays which minimizes the number of devices required and the amount of chip area used.
This objective is accomplished by using a local bit switch design which requires only a single N channel field effect transistor in each sense amplifier bank.


REFERENCES:
patent: 5812473 (1998-09-01), Tsai
patent: 5822268 (1998-10-01), Kirihata
patent: 5923605 (1999-07-01), Mueller et al.
patent: 5940329 (1999-08-01), Seitsinger et al.
patent: 5949732 (1999-09-01), Kirihata
patent: 5968913 (1999-11-01), Childers et al.

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