Local bit select with suppression of fast read before write

Details Local bit select with suppression of fast read before write Local bit select with suppression of fast read before write

2006-09-26

2006-09-26

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Read/write circuit

For complementary information

C365S154000, C365S156000, C365S189060, C365S189110

Reexamination Certificate

active

07113433

ABSTRACT:
A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors. Separate read and write global “bit line” pairs allow the read and write performance to be optimized independently.

REFERENCES:
patent: 5831911 (1998-11-01), Cho
patent: 5850367 (1998-12-01), Wada et al.
patent: 5973973 (1999-10-01), Utsugi
patent: 5986914 (1999-11-01), McClure
patent: 6088276 (2000-07-01), Ukita
patent: 6292408 (2001-09-01), Kawashima et al.
patent: 6751141 (2004-06-01), Alvandpour et al.
patent: 6839268 (2005-01-01), Osada et al.
patent: 6930941 (2005-08-01), Nakase

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