Local bit select circuit with slow read recovery scheme

Details Local bit select circuit with slow read recovery scheme Local bit select circuit with slow read recovery scheme

2006-09-05

2006-09-05

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S154000, C365S156000, C365S190000, C365S208000

Reexamination Certificate

active

07102946

ABSTRACT:
Local bit line pairs in a domino SRAM include an amplifier to amplify the voltage differential across the bit lines during a read operation if a cell in the local group of cells has been identified as a slow to read cell. The amplifier includes a transistor switch that is turned on by a timing pulse during the read operation, but only if the Array Built In Self-Test (ABIST) has detected a slow to read cell in the local group. If there is no slow cell, the amplifier is not activated, and the domino read operation is carried out. The amplifier can be used globally across the SRAM or selectively in certain sub-arrays.

REFERENCES:
patent: 4400800 (1983-08-01), Kurafuji
patent: 5719811 (1998-02-01), Kondou
patent: 6275433 (2001-08-01), Forbes

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