Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
2001-12-31
2004-12-21
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S519000, C345S098000
Reexamination Certificate
active
06833832
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to display systems that use spatial light modulators, and more particularly, to storing data for delivery to the spatial light modulator.
BACKGROUND OF THE INVENTION
Video display systems based on spatial light modulators (SLMs) are increasingly being used as an alternative to display systems using cathode ray tubes (CRTs). SLM systems provide high resolution displays without the bulk and power consumption of CRT systems.
Digital micro-mirror devices (DMDs) are a type of SLM, and may be used for projection display applications. The images provided by a DMD compare favorably with those provided by CRTs and can be projected to a screen in dimensions surpassing today's large screen televisions.
A DMD has an array of micro-mechanical display elements, each having a tiny mirror that is individually addressable by an electronic signal. Depending on the state of its addressing signal, each mirror tilts so that it either does or does not reflect light to the image plane, thereby modulating light incident on the DMD. The mirrors may be generally referred to as “display elements”, which correspond to the pixels of the image that they generate. Generally, displaying pixel data is accomplished by loading memory cells connected to the display elements. Each memory cell receives one bit of data representing an on or off state of the display. The display elements can maintain their on or off state for controlled display times.
Other SLMs operate on similar principles, with an array of display elements that may emit or reflect light simultaneously, such that a complete image is generated by addressing display elements rather than by scanning a screen. Another example of an SLM is a liquid crystal display (LCD) having individually driven display elements.
For all types of SLMs, motion displays are achieved by updating the data in the SLM's memory cells at sufficiently fast rates. To achieve intermediate levels of illumination, between white (on) and black (off), pulse-width modulation (PWM) techniques are used. The basic PWM scheme involves first determining the rate at which images are to be presented to the viewer. This establishes a frame rate and a corresponding frame period. For example, if images are displayed 60 frames per second, each frame lasts for approximately 16.7 milliseconds. Then, the intensity resolution for each pixel is established. In a simple example, and assuming n bits of resolution, the frame time is divided into 2
n
−1 equal time slices. For a 16.7 millisecond frame period and n-bit intensity values, the time slice is 16.7/(2
n
−1) milliseconds.
Having established these times, for each pixel of each frame, pixel intensities are quantized, such that black is 0 time slices, the intensity level represented by the LSB is 1 time slice, and maximum brightness is 2
n
−1 time slices. Each pixel's quantized intensity determines its on-time during a frame period. Thus, during a frame period, each pixel with a quantized value of more than 0 is on for the number of time slices that correspond to its intensity. The viewer's eye integrates the pixel brightness so that the image appears the same as if it were generated with analog levels of light.
For addressing SLMs, PWM calls for the data to be formatted into “bit-planes”, each bit-plane corresponding to a bit weight of the intensity value. Thus, if each pixel's intensity is represented by an n-bit value, each frame of data has n bit-planes. Each bit-plane has a 0 or 1 value for each display element. In the PWM example described in the preceding paragraphs, during a frame, each bit-plane is separately loaded and the display elements are addressed according to their associated bit-plane values. For example, the bit-plane representing the LSBs of each pixel is displayed for 1 time slice, whereas the bit-plane representing the MSBs is displayed for 2 n/2 time slices.
The task of providing data to the SLM is further complicated by efforts to achieve the best picture quality. To this end, various “bit-splitting” sequences have been devised. These sequences distribute within the frame period, the longer display times associated with the more significant bits. For example, rather than turning the MSB on or off for a contiguous block of time, its time is divided and interspersed among the display times of other bits. As a simple example, the MSB time could be divided in half, with one half being displayed at the beginning of the frame, followed by the display times of some of the other bits, with the rest of the MSB time at mid-frame, followed by the display times of the remaining bits.
SUMMARY OF THE INVENTION
One aspect of the invention is a controller for a spatial light modulator (SLM) that receives pixel data formatted into bit-plane data. The controller determines which bit-planes are sent to external memory and which bit-planes are sent to an “MSB” local memory. Typically, the bit-planes stored in the “MSB” local memory are sent to the SLM more often. This greatly reduces the bandwidth requirements of the external memory interface. The controller will then manage receiving the data from both the external frame memory and the “MSB” local memory for display on the SLM. This will typically be accomplished with additional local memory so that maximum burst rates can be achieved. A physical layer interface provides for the transfer of data from this local memory to the SLM at high data transfer rates. The rest of the controller comprises various hardware for controlling the operation of the SLM.
An advantage of the invention is that it reduces the bandwidth required for data transfers from external frame memory to the SLM. It is a solution to the task of transferring data that achieves a low system cost and meets acceptable load times for the SLM.
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patent: 5452024 (1995-09-01), Sampsell
patent: 5526051 (1996-06-01), Gove et al.
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patent: 6388661 (2002-05-01), Richards
patent: 6525720 (2003-02-01), Baek
Brady III Wade James
Brill Charles A.
Tung Kee M.
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