Loading the input memory of an LDPC decoder with data for...

Details Loading the input memory of an LDPC decoder with data for... Loading the input memory of an LDPC decoder with data for...

2011-06-21

2011-06-21

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S786000, C714S794000, C714S795000, C375S341000, C375S262000

Reexamination Certificate

active

07966544

ABSTRACT:
An input memory of an LDPC decoder is loaded with data corresponding to an LDPC frame to be decoded and including N LLRs, of which K are information LLRs and N−K are parity LLRs. At least one stream is formed of binary words of a first type, each corresponding to multiple information LLRS, with the aid of a serial/parallel conversion module, and at least one stream is formed of binary words of a second type, each corresponding to multiple parity LLRs, with the aid of a row/column interlacing device comprising a two-dimensional first-in first-out ring buffer. The first memory accesses are made in page mode in order to write the binary words of the first type to a first zone of the input memory, and the second memory accesses are made in page mode in order to write the binary words of the second type to a second zone.

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