Loading element for a logic gate

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor

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Details

326112, 327314, 327 52, H03K 19094, H03K 1920, H03F 345

Patent

active

059202050

ABSTRACT:
A loading arrangement for an input stage of a source coupled logic gate comprises a loading element having at least one resistive element and at least one voltage limiting element connected in parallel with one another. There is also disclosed a loading arrangement comprising resistive and voltage limiting elements connected in parallel.

REFERENCES:
patent: 5483183 (1996-01-01), Li et al.

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