Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1998-12-18
2000-12-05
Tokar, Michael
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 38, 326 39, G06F 738
Patent
active
061572098
ABSTRACT:
In an FPGA having four-input lookup tables (LUTs) with parallel two-input AND gates receiving two of the four LUT input signals, associated registers, and a carry chain receiving one input signal from the AND gate output, a loadable up-down counter is formed by connecting the register output to one of the terminals serving as both a LUT input terminal and an AND gate input terminal. A load control signal is connected to another input terminal common to the LUT and the AND gate. Thus the AND gate disables the carry chain during loading of the counter and applies the count value to the carry chain during counting.
REFERENCES:
patent: 5682107 (1997-10-01), Tavana et al.
patent: 5889411 (1999-03-01), Chaudhary
patent: 5920202 (1999-07-01), Young et al.
Xilinx, Inc., "Libraries Guide, Xilinx Development System," Jan. 1998, pp. 3-89 through 3-91, 3-93.
Brown, Esq. Scott R.
Tokar Michael
Tran Ann
Xilinx , Inc.
Young Edel M.
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