Load when reservation lost instruction for performing...

Details Load when reservation lost instruction for performing... Load when reservation lost instruction for performing...

2006-03-16

2009-08-25

Bataille, Pierre-Michel (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S152000, C711S154000, C711S156000

Reexamination Certificate

active

07581067

ABSTRACT:
A load when reservation lost instruction for performing cacheline polling is disclosed. Initially, a first process requests an action to be performed by a second process. The request is made via a store operation to a cacheable memory location. The first process then reads the cacheable memory location via a conditional load operation to determine whether or not the requested action has been completed by the second process, and the first process sets a reservation at the cacheable memory location if the requested action has not been completed by the second process. The conditional load operation of the first process is stalled until the reservation at the cacheable memory location has been lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.

REFERENCES:
patent: 4380798 (1983-04-01), Shannon et al.
patent: 5611074 (1997-03-01), Kantz et al.
patent: 2003/0115476 (2003-06-01), McKee

Affiliated with

Also associated with

Rating

Load when reservation lost instruction for performing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Load when reservation lost instruction for performing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Load when reservation lost instruction for performing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4069135