Load testing apparatus, computer readable recording medium...

Details Load testing apparatus, computer readable recording medium... Load testing apparatus, computer readable recording medium...

2006-11-14

2006-11-14

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S012000, C714S030000

Reexamination Certificate

active

07137035

ABSTRACT:
In a load testing apparatus, before the load test, three processor elements are combined, without overage or shortage, with a source processor element and a destination processor element as one pair, and the transmission time between the processor elements for each pair is measured. During the load test, packets are sent at a time from the source processor element to the corresponding destination processor element in the same pair, and the transmission time for each pair is measured. The transmission time measured for each pair in the load test is compared with a corresponding expected value data so as to evaluate the performance.

REFERENCES:
patent: HEI 3-238951 (1991-10-01), None
patent: HEI 4-256260 (1992-09-01), None
patent: HEI 7-129522 (1995-05-01), None
patent: HEI 7-183899 (1995-07-01), None
Culler, David E. Parallel Computer Architecture: A Hardware/Software Approach. (c) 1999. Morgan Kauffman Publishers, Inc. pp. 468-473, 750-755.
Culler, David E. Parallel Computer Architecture: A Hardware/Software Approach. (c) 1999. Morgan Kauffman Publishers, Inc. pp. 789-790.

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