Load/store unit implementing non-blocking loads for a superscala

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

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711118, 711144, G06F 1200

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058025880

ABSTRACT:
A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Memory operations are selected from the load/store buffer for access to the data cache, including cases where the memory operation selected is subsequent in program order to a memory operation which is known to miss the data cache and is stored in the buffer. In this way, other memory operations that may be waiting for an opportunity to access the data cache may make such accesses, while the memory operations that have missed await an opportunity to make a main memory request. Memory operations that have missed are indicated by a miss bit being set, so that the mechanism which selects memory operations to access the data cache may ignore them until they become non-speculative.

REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4370710 (1983-01-01), Kroft
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 5179679 (1993-01-01), Shoemaker
patent: 5185871 (1993-02-01), Frey et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5333276 (1994-07-01), Solari
patent: 5353426 (1994-10-01), Patel et al.
patent: 5375216 (1994-12-01), Moyer et al.
patent: 5379396 (1995-01-01), Gochman et al.
patent: 5418973 (1995-05-01), Ellis et al.
patent: 5434987 (1995-07-01), Abramson et al.
patent: 5450564 (1995-09-01), Hassler et al.
patent: 5454117 (1995-09-01), Puziol et al.
patent: 5455924 (1995-10-01), Shenoy et al.
patent: 5471598 (1995-11-01), Quattromani et al.
patent: 5517657 (1996-05-01), Rodgers et al.
patent: 5524263 (1996-06-01), Griffith et al.
patent: 5526510 (1996-06-01), Akkary et al.
patent: 5555392 (1996-09-01), Chaput et al.
patent: 5557763 (1996-09-01), Senter et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.
Blount, F.T. et al. "Deferred Cache Storing Method", IBM Technical Disclosure Bulletin, vol. 23, No. 1, pp. 262-263, Jun. 1980.
Pierce, Jim and Trevor Mudge. "The Effect on Speculative Execution on Cache Performance", Parallel Processing 1994 Symposium, 1994.
Farkas, Keith I. et al. "How Usefule Are Non-blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processor?", High Performance Computer Architecture, 1995 Symposium, 1995.
Farkas, Keith I. and Norman P. Jouppi. "Complexity/Performance Tradeoffs with Non-Blocking Loads", Computer Architecture, 1994 International Symposium, 1994.
Popescu, Val et al. "The Metaflow Architecture". IEEE Micro, Jun. 1991.
Johnson, Mike. Superscalar Microprocessor Design. Prentice Hall, 1991, pp. 1-289.
Diefendorff, Kieth and Michael Allen. "Organization of the Motorola 88110 Superscalar RISC Microprocessor", IEEE Micro, Apr. 1992.

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