Load register instruction short circuiting method

Details Load register instruction short circuiting method Load register instruction short circuiting method

2011-03-08

2011-03-08

Kindred, Alford W (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Scoreboarding, reservation station, or aliasing

C711S113000

Reexamination Certificate

active

07904697

ABSTRACT:
An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.

REFERENCES:
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patent: 5542075 (1996-07-01), Ebcioglu et al.
patent: 5887161 (1999-03-01), Cheong et al.
patent: 6189088 (2001-02-01), Gschwind
patent: 6594754 (2003-07-01), Jourdan et al.
patent: 6697933 (2004-02-01), Pribush et al.

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