Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2003-05-09
2008-03-11
Bataille, Pierre (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07343456
ABSTRACT:
A node includes a processor coupled to an interconnect and a memory bridge coupled to the interconnect. The processor is configured to maintain a first indication of whether or not a modification of data at a first address has been detected by the processor after a most recent load-linked (LL) instruction was executed by the processor to the first address. The memory bridge is responsible for internode coherency within the node, and is configured to initiate a first transaction on the interconnect in response to receiving a probe command from another node. The processor is configured, during a time period in which the processor has a second transaction outstanding to the first address, to change the first indication to the first state responsive to the first transaction.
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Bataille Pierre
Broadcom Corporation
Garlick & Harrison & Markison
Tsai Sheng-Jen
LandOfFree
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