Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2000-05-31
2002-06-18
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C327S295000, C333S109000, C326S093000, C710S108000
Reexamination Certificate
active
06407575
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to clock sources used in multiprocessor computers and, in particular, to a synchronous reference clock source used in a distributed multiprocessor system having a plurality of nodes, each of which may be “hot-swapped”.
BACKGROUND OF THE INVENTION
A multiprocessor computer may comprise a plurality of subsystems or “nodes” that are interconnected to form a system with high processor counts. Each multiprocessor node may contain a plurality of components, such as processors, memory and an input/output (I/O) subsystem. The I/O subsystems are further interconnected to enable communication between the nodes. The multiprocessor system is a synchronous system; that is, a global signal source of the system generates and provides periodic signals to the nodes in “synchronization,” i.e., at the same time. The global signal source may comprise a sinusoidal radio-frequency source configured to generate sinewave clock signals for distribution among the nodes.
The synchronous multiprocessor system may further comprise a “high availability” system that supports “hot-swap” (i.e., an insertion or removal) of a node while the remaining nodes of the system continue to operate. Insertion or removal of a load from an operating synchronous multiprocessor system having a global signal source generally causes the clock system to fail (i.e., become non-synchronous). Failure of the clock system may arise because of interactions between properly terminated clock branches of the clock system and an improperly terminated clock branch caused by hot-swapping of a clock branch load. In addition to a node, the clock branch load may comprise a system module or a collection of modules within the multiprocessor system.
Hot-swapping a node within a multiprocessor system is a relatively recent concept, particularly with respect to a system having a global sinewave clock source. Nevertheless, the present state of the art does not teach a method of notifying the global clock source prior to a node being removed or added from the system. That is, the multiprocessor system generally has no active system control over the global clock system that can deselect a clock branch before the clock load is removed. The global signal source must therefore be configured to electrically withstand physical insertion or removal of a node from the system without interrupting operation of remaining (“neighboring”) nodes operating within the system.
However, an approach to inserting a node into a running synchronous multiprocessor system may involve activating the clock signals provided to the inserted node from the global signal source so that the clock signals arrive at the inserted node in synchronization with the clock signals, supplied to the neighboring node. This activation method is somewhat difficult and complicated because the time needed for the clock signals to propagate to the components of the inserted node must be determined prior to supplying the clock signals to the inserted node. Furthermore, the time needed for the clock signals to “lock onto” clock-supporting circuitry, such as phase lock loops (PLLs), must be determined. Once the PLLs have locked to the reference clock signals, the inserted node may then be powered up such that each of its constituent components is activated.
The activation method is indeterministic and, therefore, generally undesirable. Moreover, extensive circuitry may be required within each node to determine when the reference clock signals supplied to the components of the node are in synchronization. This information is needed so that system software may be notified to allow the inserted node to become part of the operating system set of the multiprocessor system. The present invention is directed to a load-insensitive clock source that enables efficient hot-swap of a node from an operating synchronous multiprocessor system.
SUMMARY OF THE INVENTION
The present invention comprises a novel circuit that enables a global reference clock source of a synchronous multiprocessor system having a plurality of nodes to be “insensitive” with respect to the insertion or removal (“hot-swap”) of a load (such as a node) when the system is operational. In particular, the load insensitive clock source is provided through the use of a customized two-way passive radio frequency (RF) power splitter having an input port and two phase-matched output ports. A high degree of isolation is provided between clock signals delivered over the output ports when the input port of the splitter is properly terminated and embedded in a controlled impedance environment. Isolation is further enhanced by terminating each output port with a constant impedance. According to the present invention, the constant impedance comprises a precisely-matched, 50-ohm impedance load pad.
Advantageously, the inventive circuit allows the global reference clock source to be “load insensitive”. By providing such a load insensitive global clock source, synchronous interaction between the hot-swapped node and its neighboring node of the multiprocessor system is not required.
REFERENCES:
patent: 5519362 (1996-05-01), Li et al.
patent: 6184736 (2001-02-01), Wissell et al.
patent: 6239387 (2001-05-01), Wissell
Checkowski George S.
Wissell Daniel
Cesari and McKenna LLP
Chang Daniel D.
Compaq Computer Corporation
Paul, Esq. Edwin H.
Tokar Michael
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