Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-03-27
2003-07-22
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C327S053000, C327S066000
Reexamination Certificate
active
06597613
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuits, and more particularly, to apparatuses and methods for load independent single ended sense amplifiers in programmable read only memory.
2. Description of the Related Art
Semiconductor memory devices are widely used in the manufacture of digital equipment, such as microprocessor systems. To store fixed, commonly used programs, microprocessor systems generally use Read Only Memory devices or “ROMs,” such as the basic input/output system (BIOS) ROM for computer systems.
Semiconductor ROMs are typically configured as an array memory cells, wherein each individual memory cell is coupled to both a wordline and a bitline. To select a particular memory cell during a read operation, memory accessing circuitry is commonly utilized. For example, memory access circuit components typically include addressing circuitry for selecting a memory cell, wordline drivers for driving a selected wordline, sense amplifiers for amplifying the signals read from the selected memory cell, and output buffers for driving data out of the memory.
FIG. 1A
shows a conventional ROM addressing block diagram used for accessing digital data stored within a ROM core
100
. Typically, host computers access the ROM core
100
through an address input bus
110
that may be coupled to an X-DECODER
102
and a Y-DECODER
104
. In general, X-DECODER
102
is used for addressing a selected row within ROM core
100
, and Y-DECODER
102
is used for addressing a selected column within ROM core
100
. Often, the X and Y decoders are implemented for reducing memory array aspect ratios by folding (i.e., dividing) long addressable memory columns into several shorter memory columns. Once folded into several columns, the X and Y decoders are capable of accessing the addressed data by appropriately performing a suitable multiplexing function.
Once a row and column is selected from ROM core
100
, a very low voltage, which may be as low as 20 milli-volts (mV), can be sensed on a data bus
112
representing the addressed data. To appropriately read the addressed data, suitable amplification is performed using a sense amplifier
106
. Once the sensed data signal is amplified to about 3.3 volts or about 5 volts in sense amplifier
106
, the voltage amplified data (i.e., digital data) is passed through as an amplified data output
114
to an output buffer
108
. At output buffer
108
, the voltage amplified data is current amplified to provide an appropriate level of current drive once the read data is passed to a ROM output bus
116
.
FIG. 1B
illustrates a conventional single ended differential pair sense amplifier
106
. As shown, sense amplifier
106
includes a rail voltage (Vcc) which is typically about 3.3 volts or 5 volts connected to a transistor
122
and a transistor
120
that form a current mirror. Connected to the current mirror transistors is a gain transistor
126
and a gain transistor
124
. A gate of gain transistor
124
is coupled to a V
REF
, which is typically about Vcc/2. Further, a gate of gain transistor
126
is shown interfacing with ROM core
100
via data bus
112
. Coupled between transistor
122
and gain transistor
126
is amplified data output
114
that feeds to output buffer
108
where appropriate current amplification is performed.
Generally, the conventional single ended differential pair ROM architecture works well for applications in which low power consumption is not of any particular concern. However, in applications where low power consumption is needed, the high power consuming response of sense amplifier
106
may not be acceptable. Accordingly, sense amplifier
106
is not well suited for use in portable electronic devices that critically depend on a batteries limited useful life. As an example, many modern hand-held portable electronics devices such as laptop computers, pen-based computers and cellular phones, are many times rendered useless when memory accessing operations drain the electronic device's battery.
In addition, the conventional single ended differential pair ROM architecture requires considerable logic, both internal and supporting, to function properly. As a result, the conventional single ended differential pair ROM architecture requires a large area of the ROM. In view of the foregoing, there is a need for a sense amplifier that is low power consuming and has a reduced area for use in memory accessing operations. To this end, the sense amplifiers should provide high speed sensing, which is low power, load independent, and requires a reduced area for implementation.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a load independent single ended sense amplifier. In one embodiment, a sense amplifier for amplifying bitline current is disclosed. The sense amplifier includes a first current mirror having a first load transistor and a first reflected current transistor, and a second current mirror having a second load transistor and a second reflected current transistor. The first load transistor is capable of communicating a load current to the second load transistor. In addition, a reflected current flowing through the first reflected current transistor and the second reflected current transistor generates an amplified load current. In one aspect, a drop in the load current across the first load transistor can be configured to increase the current in the first reflected current transistor. In addition, the drop in the load current across the first load transistor can be configured to reduce the current in the second load transistor thereby reducing the current in the second reflected current transistor.
In another embodiment, a ROM is disclosed that includes a sense amplifier for amplifying bitline current. The ROM includes a memory cell array having a depth that is defined by a plurality of wordlines and a width that is defined by a plurality of bitlines. In addition, a first current mirror including a first load transistor and a first reflected current transistor is included, where the first load transistor is in electrical communication with a bitline. A second current mirror is also included that has a second load transistor and a second reflected current transistor. The first load transistor is capable of communicating a load current to the second load transistor, and a reflected current flowing through the first reflected current transistor and the second reflected current transistor generates an amplified load current.
A further sense amplifier for amplifying bitline current is disclosed in a further embodiment of the present invention. The sense amplifier includes an isolation transistor that is in electrical communication with a bitline. Similar to above, a first current mirror is included that has a first load transistor and a first reflected current transistor. Both the first load transistor and the first reflected current transistor are p-type transistors. Also, the first load transistor is capable of receiving a load current from the isolation transistor. A second current mirror is also included that has a second load transistor and a second reflected current transistor. The second load transistor and the second reflected current transistor are n-type transistors. The first load transistor is capable of communicating the load current to the second load transistor. Further, a reflected current flowing through the first reflected current transistor and the second reflected current transistor generates an amplified load current. In one aspect, the gate and drain of the first load transistor can be coupled together. Also, the gate and drain of the second load transistor can be coupled together. In a further aspect, reflected current flow through the first reflected current transistor is increased and the reflected current flow through the second reflected current transistor is reduced when a “0” core cell on the bitline is addressed.
Advantageously, the embodiments of the present invention are highly tuna
Becker Scott T.
Hold Betina
Moharir Sudhir S.
Artisan Components Inc.
Martine & Penilla LLP
Nguyen Tan T.
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