Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
1999-09-01
2001-07-24
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000, C327S170000, C326S087000, C330S085000
Reexamination Certificate
active
06265913
ABSTRACT:
RELATED APPLICATION
This application is related to Korean Application No. 98-36292, filed Sep. 3, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices in general and, more particularly, to load driving circuits.
BACKGROUND OF THE INVENTION
Load driving circuits, such as output buffers of an integrated circuit, may be used to drive large capacitive loads. Such output buffers may be relatively large to provide the capacity to drive large capacitive loads. For example, if a large capacity load is electrically coupled to the output, a large pull-down device may be able to pull-down the voltage level at the load faster than a smaller pull-down device.
Moreover, some conventional output buffers may be subject to noise when switching large loads and/or switching a large number of loads simultaneously. The noise can be generated by parasitic inductance of wires electrically coupled to the output. The noise generated by parasitic inductance of wires can combine with noise generated by the capacitance of the load to cause oscillations at the output of the buffer. Consequently, the output speed of the output buffer may be reduced and if the oscillation of the signal exceeds the noise margin of the output buffer circuit, the output buffer may malfunction.
FIG. 1
is a circuit diagram of a conventional output buffer. Referring to
FIG. 1
, the conventional output buffer includes a pull-up transistor
111
, a pull-down transistor
112
, and logic devices
113
through
117
. The pull-up transistor
111
is electrically coupled to an external bus line via an output OUT. The pull-up transistor
111
pulls the voltage level at the output OUT up in response to a first output signal of the logic gate
114
. The pull-down transistor
112
is electrically coupled to the output OUT and pulls the voltage level at the output OUT down in response to a second output signal of the logic gate
117
. The pull-down transistor
112
can be large relative to the pull-up transistor
111
. Reference designators DB and EN denote output data and an enable signal for the output buffer respectively.
In the case of a multi-bit semiconductor memory device, the problems described above can become more serious due to the simultaneous switching of outputs. Therefore, it may be beneficial to reduce the magnitude of the noise related to the switching speed of the output buffer by reducing the rate of change of the current.
It is known to apply a low voltage level to the gate of an NMOS transistor of the output buffer in an initial stage and apply a power supply voltage after a certain time has passed to reduce the rate of change of the current. Such techniques are discussed, for example, in an article by Miyaji, entitled
A
25
ns
4
Mbit CMOS SRAM with dynamic bit-line loads,
IEEE J. Solid-State Circuits, vol. 24, pp. 1213-1217, October 1989.
It is also known to provide an NMOS transistor and a PMOS transistor of the output buffer are comprised of N transistors electrically coupled in parallel and time taken to turn on the respective transistor is controlled. Such techniques are discussed, for example, in an article by Senthinathan entitled
Application specific CMOS output driver circuit design technique to reduce simultaneous switching noise,
in IEEE J. Solid-State Circuits, Vol. 28, pp. 1383-1388, December 1993. Unfortunately, according to the techniques discussed in Miyaji and Senthinathan, it may not be possible to know the load conditions in advance.
It is also known to control the output current of the output buffer by designating a slow mode and a fast mode from the outside according to the load condition of the output. Control of fast and slow modes is discussed, for example, in an article by Furutani entitled
Adjustable output driver with a self-recovering Vpp generator for a
4
M×
16
DRAM
, in IEEE J. Solid-State Circuits, Vol. 19, pp. 308-310, March 1994. Unfortunately, according to the techniques discussed in Furutani, additional pins may be needed on the device in order to designate the load condition external to the device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit output buffers.
It is another object of the present invention to provide integrated circuit output buffers having improved simultaneous-switching noise characteristics.
These and other objects are provided by a buffer that includes a first and a second pull-down device therein electrically coupled in parallel between an output and a reference signal line. A load sensing circuit is electrically coupled to the output buffer and to the second pull-down device. The load sensing circuit disables the second pull-down device if a load capacitance, electrically coupled to the output of the buffer, is less than a threshold capacitance and enables the second pull-down device if the load capacitance is greater than the threshold capacitance. Accordingly, the enabled pull-down devices adjust the current driving capacity of the load driving circuit. Adjusting the current driving capacity can control the rate of change of the current conducted by the load driving circuit and, thereby, may reduce noise associated with driving the load.
In another aspect of the present invention, the load sensing circuit includes a reference capacitor and a comparator circuit that is electrically coupled to the first reference capacitor. The load sensing circuit generates a signal to enable the second pull-down device if the load capacitance is greater than the threshold capacitance.
In a further aspect of the present invention, the comparator circuit generates a signal to enable the second pull-down device if the load capacitance is greater than a reference capacitance of a reference capacitor value.
In yet another aspect of the present invention, the pull-down device includes first and second pull-down transistors and a delay circuit having an input electrically coupled to a gate electrode of the first pull-down transistor and an output electrically coupled to a gate electrode of the second pull-down transistor.
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Furutani et al., “An Adjustable Output Driver with a Self-Recovering Vpp Generator for a 4M X 16 DRAM,” IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994, pp. 308-310.
Miyaji et al., “A 25-ns 4-Mbit CMOS SRAM with Dynamic Bit-Line Loads,” IEEE Journal of Solid-State Circuits, vol., 24, No. 5, Oct. 1989, pp. 1213-1218.
Senthinathan et al., “Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise,” IEEE, Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993, pp. 1383-1388.
Kim Wen-Chun
Lee Dong-yun
Lee Seung-wook
Cunningham Terry D.
Myers Bigel & Sibley & Sajovec
Nguyen Long
Samsung Electronics Co,. Ltd.
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