Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1996-04-19
1998-09-01
Ramirez, Ellis B.
Static information storage and retrieval
Read/write circuit
Bad bit
G06F 1700
Patent
active
058023089
ABSTRACT:
In a first aspect of the invention, the load on a central management/control apparatus is monitored to determine a control rate appropriate to the load, and inquiries from an inquiry execution apparatus or an exchange are controlled by rejecting inquiries in proportion to the control rate. In enforcing the control, a control process is selected, in accordance with the load, from among: a control process 1 in which the inquiry execution apparatus is notified when an inquiry has been rejected; a control process 2 in which inquires are rejected without issuing a notification; a control process 3 in which the inquiry execution apparatus is instructed to control inquiries; and a control process 4 in which at least two of these control processes are combined. In a second aspect of the invention, the occurrence of an overload condition is prevented by rejecting all inquiries arising from specific calls.
REFERENCES:
patent: 4497979 (1985-02-01), Phelan
patent: 4984264 (1991-01-01), Katsube
patent: 5425086 (1995-06-01), Hidaka et al.
patent: 5442789 (1995-08-01), Baker et al.
patent: 5655120 (1997-08-01), Witte et al.
Ige Fumiyasu
Itoh Yayoi
Tanaka Tadaaki
Fujitsu Limited
Ramirez Ellis B.
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