Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-12-19
2002-03-05
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S088000, C327S143000, C327S198000, C324S678000, C324S679000, C324S676000
Reexamination Certificate
active
06353337
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a load capacitance measuring circuit for measuring the capacitance of a capacitive load of an external circuit, and to an output buffer capable of controlling its driving power in accordance with the capacitance of a capacitive load of an external circuit.
2. Description of Related Art
As a protocol for connecting a host with a device (hard disk drive), there is a standard called ATA interface. In the ATA interface, the load capacitance of an external circuit connected to an output buffer varies greatly depending on a usage mode. For example, one or two devices can be connected to a single host, and a flat cable or other cables can be used for connecting the host to the devices. These conditions can vary the load capacitance of the external circuit. In addition, since the ATA interface protocol specifies the maximum slew rate and maximum delay time of the output signal, it is necessary to provide the load driving power corresponding to the load capacitance to meet the specification. It holds true not only for the output buffers connected to the ATA interface, but also for any output buffers connected to external circuits that the output buffers with appropriate load driving power must be used to implement desired output signals in terms of rising time and the like.
FIG. 11
is a circuit diagram showing a configuration of a semiconductor integrated circuit including a conventional output buffer. In
FIG. 11
, the reference numeral
100
designates a semiconductor integrated circuit;
101
designates an internal circuit;
102
designates an output buffer;
103
designates an output terminal;
104
designates an inverter for inverting amplification; and
105
,
106
and
107
designate inverters connected in parallel with each other. In the manufacturing process, the number of the inverters connected in parallel or the channel widths of the transistors constituting the inverters are adjusted in order to adjust the load driving power of the output buffer to an appropriate level, considering the load capacitance of an external circuit to be connected to the output buffer
102
so that an output signal with suitable driving power is produced for the load capacitance.
With the foregoing configuration, the conventional output buffer has a problem of being unable to meet the specification concerning the slew rate or delay time, if the load capacitance of the external circuit is greater than the assumed load capacitance, and hence the load driving power of the output buffer is relatively small, because the heavy load hinders the output signal from providing an enough rising or falling time required.
On the other hand, if the load capacitance of the external circuit is smaller than the assumed load capacitance, the load driving power of the output buffer becomes relatively large, presenting another problem of consuming excessive power.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a load capacitance measuring circuit capable of measuring the capacitance of a capacitive load of an external circuit.
Another object of the present invention is to provide an output buffer capable of adjusting the load driving power in accordance with the capacitance of the capacitive load of an external circuit.
According to a first aspect of the present invention, there is provided a load capacitance measuring circuit comprising: a reference capacitor; a constant current source connected in series with the reference capacitor, for generating a reference voltage with a constant gradient in the reference capacitor; a load resistor; and a transistor having its source connected to a capacitive load to be measured, its gate connected to a connecting point of the reference capacitor and the constant current source to be supplied with the reference voltage, and its drain connected to a voltage source via the load resistor, wherein a capacitance of the capacitive load is obtained from the drain voltage of the transistor and the gradient of the reference voltage.
Here, a capacitance of the reference capacitor may be variable.
A constant current the constant current source outputs may be variable.
According to a second aspect of the present invention, there is provided an output buffer comprising: a reference capacitor; a first constant current source connected in series with the reference capacitor, for generating a reference voltage with a constant gradient by charging the reference capacitor; a first transistor having its source connected to a capacitive load, and its gate connected to a connecting point of the reference capacitor and the first constant current source to be supplied with the reference voltage; a first switching device connected between the drain of the first transistor and a voltage source; a second switching device connected between the capacitive load and the voltage source; and a first driver connected to a control terminal of the first switching device and to a control terminal of the second switching device, for switching the first switching device and the second switching device from an OFF state to an ON state when the first transistor is turned on.
Here, the output buffer may further comprise: a second constant current source connected in series with the reference capacitor, for changing the reference voltage at a constant rate by discharging the reference capacitor; a second transistor having its source connected to the capacitive load, and its gate connected to a connecting point of the reference capacitor and the second constant current source to be supplied with the reference voltage; a third switching device connected between the drain of, the second transistor and a ground; a fourth switching device connected between the capacitive load and the ground; and a second driver connected to a control terminal of the third switching device and to a control terminal of the fourth switching device, for switching the third switching device and the fourth switching device from an OFF state to an ON state when the second transistor is turned on.
A capacitance of the reference capacitor may be variable.
A constant current supplied from the first constant current source to the reference capacitor may be variable.
A constant current discharged from the reference capacitor by the second constant current source may be variable.
According to a third aspect of the present invention, there is provided an output buffer comprising: a reference capacitor; a first constant current source connected in series with the reference capacitor, for generating a reference voltage with a constant gradient by charging the reference capacitor; a first transistor having its source connected to a capacitive load, and its gate connected to a connecting point of the reference capacitor and the first constant current source to be supplied with the reference voltage; a first switching device connected between the drain of the first transistor and a voltage source; a second switching device connected between the capacitive load and the voltage source; and a third switching device that is connected between a control terminal of the first switching device and a control terminal of the second switching device, and controlled by a voltage across the capacitive load.
Here, the output buffer may further comprise: a second constant current source connected in series with the reference capacitor, for changing the reference voltage at a constant rate by discharging the reference capacitor; a second transistor having its source connected to the capacitive load, and its gate connected to a connecting point of the reference capacitor and the second constant current source to be supplied with the reference voltage; a fourth switching device connected between the drain of the second transistor and the ground; a fifth switching device connected between the capacitive load and the ground; and a sixth switching device that is connected between a con
Adachi Kiyoshi
Nasu Koji
Tan Vibol
Tokar Michael
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