Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-11-14
2003-01-14
Oda, Christine K. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C439S070000
Reexamination Certificate
active
06507205
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit semiconductor device test apparatus, more particularly to a load board and interface card that allows different device designs using the same package type to be tested on a single board.
BACKGROUND
After an integrated circuit semiconductor device (IC) has been manufactured and packaged, it is necessary to test the completed article to determine whether it is functional. The packaging for an IC can take different standard forms, including dual in-line pins, ball grid arrays, thin quad flat packages, and many others. Each of these packages has a different external form factor and a different pin placement. (Pins are contacts used to interface between the semiconductor device inside the package and the external circuitry with which the device will operate.) Each package type requires its own specific socket design for receiving the pins of the IC package that interface with the device inside the package. Many different IC designs can be assembled into, for instance, a standard ball grid array package.
In order to test ICs after they have been assembled into their final package, the IC is supplied with power and ground, and a specialized test computer (a tester) sends signals to the input pins of the device under test (DUT). The output pins of the DUT are monitored by the tester and signals presented on those pins by the IC in response to the tester signals are recorded while the device is exercised. The tester compares the monitored output signals to expected results for a fully functioning device of the design being tested. ICs that do not respond correctly to the tester signals are identified as non-functioning.
The same IC design can be ultimately packaged into different package types, such as ball grid array or thin quad flat pack. The IC is the same whether it is packaged in a thin quad flat pack or a ball grid array, but the external pins from the different packages are physically located in different positions. Although the tester has one set of tests unique to each IC design, there must be a way to map the tester pins to the correct pinout of the different package types into which the IC is assembled.
The prior art approach to creating an interface between the tester and the DUT is to custom design a printed circuit board (PCB) that interfaces the pins of the DUT to the pins of one or more cables connected to the tester. Each signal sent from the tester must be routed to a particular pin on the DUT. Likewise, the signal on each tested output pin of the DUT must be routed to the correct cable pin from the tester. Each IC design has a variety of pins for interfacing to other circuits. These pins include power, ground, input/output, and perhaps function control pins for putting the IC into different functional modes or other types of pins.
Thus, using the prior art approach, a unique design is necessary to interface the tester to each IC design and each package type into which that design is assembled. In the prior art approach, for each integrated circuit design a number of custom designed test PCBs (load boards) must be created, one for each package type into which the given IC design is assembled. With a custom test PCB for each package type used for each IC design, the number of test boards required to test a manufacturer's product line adds up quickly. The number of custom test boards required can also increase depending upon the volume of products being manufactured, because more than one test board can be required to meet throughput requirements of the manufacturer. Added to the overhead in creating multiple test boards, there is a cost in engineering design time and in time to manufacture the test boards.
Therefore, it is desirable to reduce the overhead associated with design time and materials for testing packaged integrated circuit devices by employing a new method that utilizes a standard load board for each IC package type that is customizable to the DUT, and thereby reduces the number of load boards required to test a manufacturer's devices and reduces the time required to develop load boards.
SUMMARY OF THE INVENTION
In accordance with the present invention, a tester to device-under-test interface is provided in which a PCB has a socket for the device under test, one or more cable connectors for cables from an IC tester, an interface matrix card slot having a plurality of contacts electrically connected to the DUT socket and the cable connector pins, and an interface matrix card having a plurality of horizontal and vertical conductors capable of being electrically connected to each other for mapping the proper connection of signals between the DUT socket and the tester cables.
REFERENCES:
patent: 4724379 (1988-02-01), Hoffman
patent: 5460531 (1995-10-01), Vivio
patent: 5705932 (1998-01-01), Fredrickson
patent: 6005403 (1999-12-01), Webster et al.
patent: 6094056 (2000-07-01), Bardsley et al.
patent: 6118286 (2000-09-01), Fredrickson
patent: 6156188 (2000-12-01), Yang et al.
Dibish Michael J.
Kang Sunae
Brown Scott R.
Cartier Lois D.
Nguyen Vincent Q.
Oda Christine K.
Williams Hovey
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