Load based cache control for satellite based CPUs

Details Load based cache control for satellite based CPUs Load based cache control for satellite based CPUs

1999-09-07

2002-08-27

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S154000, 36, C713S100000, C455S012100

Reexamination Certificate

active

06442652

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains to satellite communications, in general, and to the operation of satellite based central processing units having cache memory utilized in satellite communication systems, in particular.
BACKGROUND OF THE INVENTION
In order to increase the speed of processing within a microprocessor or central processing unit (CPU), designers implement cache memories within the microprocessor integrated circuit chip in order to compensate for the speed differential between main memory access time and processor logic. Processor logic is generally faster than main memory access time, with the result that processing speed is limited by the speed of main memory. A technique used to compensate for the mismatch in operating speeds is to employ an extremely fast small memory having an access time close to processor logic propagation delays between the CPU and main memory. This small, or cache, memory, is used to store segments of programs currently being executed in the CPU and/or temporary data frequently needed in immediate calculations. By making program instructions and data available at a rapid rate, it is possible to increase the performance of the processor.
A described in U.S. Pat. No. 5,918,247 issued to a common assignee, analysis of a large number of typical programs has shown that the references to memory during any given interval of time tend to be confined within a few localized areas in memory. This phenomenon is sometimes referred to as the property of “locality of reference.” The reason for this property may be understood by considering that a typical computer program flows in a straight-line fashion with program loops and subroutine calls encountered frequently. When a program loop is executed, the CPU repeatedly refers to the set of instructions in memory that constitute the loop. Every time given subroutine is called, its set of instructions are fetched from memory. Thus, loops and subroutines tend to localize the reference to memory for fetching instructions.
If the active portions of the program and/or data are placed in a fast small memory, the average memory access time can be reduced, thus reducing the total execution time of the program. Such a fast small memory may be a cache memory or a buffer. Such a cache or buffer memory has an access time that is less than the access time of main memory, often by a factor of five to ten.
The fundamental idea of such a cache or buffer memory organization is that by keeping the most frequently accessed instructions and/or data in this fast cache or buffer memory, the average memory access time will approach the access time of the cache or buffer memory.
One problem with utilizing semiconductor components, such a microprocessors or CPUs, in a space environment is that the CPUs will be subjected to high energy rays or particles/ions. The geometries of newer integrated circuits are so small that passage of a high energy particle/ion or cosmic ray through a junction of a semiconductor device can cause an upset in the operation of the device. In such an environment, the presence of high energy rays or particles/ions causes random errors to occur in semiconductor devices. This problem is especially recurrent in semiconductor devices that have chips utilizing less than 3 micron geometry.
In memory systems, when a cosmic ray or high energy particle/ion passes through a sensitive junction of a storage element internal to a circuit, the result is an arbitrary change in the state of that storage element, i.e., a stored bit changes from a “zero” state to a “one” state, or vice versa. This phenomenon of a “one” change of state is called a “single event upset” (SEU). SEU is temporary in nature and disappears when the memory is reused for storing a new bit.
Due to severe irradiation effects occurring in the space environment, commercial processors can be vulnerable to the effects of SEU, which cause processor memory to become temporarily corrupted or changed. The more memory in a processor, the more susceptible it is to upset. Computer cache memory is a particularly SEU-sensitive component of a microprocessor or CPU used in space. Therefore, cache memories are often not used in satellite computers.
Not having a cache memory is a serious performance penalty to processors. Instruction and data cache memories can provide up to ten times performance improvement over similar non-cache memory operations. Therefore, non-cache memory operations can limit system capacity, performance and features offered by a given satellite.
Another way to avoid the effects of SEUs has been to use radiation hardened devices. Because the newest semiconductor devices having cache memory are not radiation hardened, satellite-based CPUs are often not the most recent commercial product.


REFERENCES:
patent: 5257360 (1993-10-01), Schnizlein et al.
patent: 5845310 (1998-12-01), Brooks
patent: 6081868 (2000-06-01), Brooks

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