Load balanced interrupt handling in an embedded symmetric...

Details Load balanced interrupt handling in an embedded symmetric... Load balanced interrupt handling in an embedded symmetric...

2002-09-27

2008-10-28

Ho, Andy (Department: 2194)

Electrical computers and digital processing systems: virtual mac

Task management or control

Process scheduling

C710S260000

Reexamination Certificate

active

07444639

ABSTRACT:
In an embedded symmetric multiprocessor (ESMP) system it is desirable to maintain equal central processing unit load balance. When an interrupt occurs, a single central processing receives the interrupt and then passes information to the central processing unit scheduling software. This software will in turn determine which central processing unit can best handle the interrupt. Because the scheduling software is able to determine which central processing unit handles the interrupt process, it can maintain central processing unit load balancing resulting in better system performance.

REFERENCES:
patent: 5867706 (1999-02-01), Martin et al.
patent: 5905897 (1999-05-01), Chou et al.
patent: 6189065 (2001-02-01), Arndt et al.
patent: 6738847 (2004-05-01), Beale et al.
patent: 6813665 (2004-11-01), Rankin et al.
patent: 2005/0102677 (2005-05-01), Gootherts

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