Load-adapted clock generator in CMOS circuits

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307262, 307279, 307479, 307510, 307272R, 3072721, 307291, 328 57, 328 62, H03K 513, H03K 500, H03K 301, H03K 3284

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047615680

ABSTRACT:
A clock generator for CMOS circuits for producing two non-overlapping internal clocks or timing cycles at two clock outputs, the clock generator having a frequency divider energized by an oscillator and having an output side, and a bistable multivibrator connected to the output side of the frequency divider and having complementary outputs includes an equal number of inverter-driver stages connected to each of the complementary outputs and being controllable thereby, the driver stages being dimensioned asymmetrically.

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patent: 4623801 (1986-11-01), Rocchi
patent: 4625126 (1986-11-01), Tinker et al.
IBM Technical Disclosure Bulletin, vol. 22, No. 3, Aug. 1979, pp. 1093-1094.

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