Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2009-02-26
2010-12-28
Stiglic, Ryan M (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S200000, C710S241000
Reexamination Certificate
active
07861022
ABSTRACT:
A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.
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Johns Charles R.
Krolak David J.
Liu Pei-chun P.
Ng Alvan W.
International Business Machines - Corporation
Stiglic Ryan M
Talpis Matthew B.
Tkacs Stephen R.
Walder, Jr. Stephen J.
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