Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-31
2010-10-26
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07823099
ABSTRACT:
A fast method to detect hot spots using foundry independent models that do not require RET/OPC synthesis is presented. In some embodiments of the present invention, sensitive spots are located. Lithography models are used to simulate the geometry near the sensitive spots to produce a model of the area around the sensitive spots. The sensitive spots are scored using a measure such as intensity (of light) or scoring based on contrast.
REFERENCES:
patent: 7448012 (2008-11-01), Qian
patent: 2005/0132322 (2005-06-01), Inoue
patent: 2007/0044049 (2007-02-01), Adams et al.
patent: 2007/0266362 (2007-11-01), Lai et al.
patent: 2008/0295046 (2008-11-01), Su et al.
Chiang Charles C.
Tsai Min-Chun
Mao Edward S.
Siek Vuthe
Silicon Valley Patent & Group LLP
SYNOPSYS, Inc.
LandOfFree
Lithography suspect spot location and scoring system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Lithography suspect spot location and scoring system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lithography suspect spot location and scoring system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4212469