Lithography simulation method, program and semiconductor...

Details Lithography simulation method, program and semiconductor... Lithography simulation method, program and semiconductor...

2007-05-24

2010-11-09

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07831953

ABSTRACT:
A lithography simulation method which predicts the result that a pattern formed on a mask is transferred onto a sample by use of a simulation based on pattern data of the mask includes subjecting a mask layout containing a pattern whose periodicity is disturbed to the simulation. At this time, a calculation area of pattern data used for the simulation is set to an integral multiple of minimum periodic length of the mask layout.

REFERENCES:
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patent: 2004/0115541 (2004-06-01), Yamaguchi et al.
patent: 2006/0078805 (2006-04-01), Hansen
patent: 2006/0129967 (2006-06-01), Tanaka et al.
V. Ivin et al., “Fast Modeling of 3D Planar Resist Images for High NA Projection Lithography,” SPIE vol. 3051, pp. 567-577.

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