Lithography method for forming semiconductor devices on a...

Details Lithography method for forming semiconductor devices on a... Lithography method for forming semiconductor devices on a...

2001-03-08

2003-09-16

Young, Christopher G. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Registration or layout process other than color proofing

C430S030000

Reexamination Certificate

active

06620563

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to large scale integration semiconductor devices and in particular, though not exclusively, to a lithography method for forming at least one semiconductor device on a wafer and an apparatus for it.
BACKGROUND OF THE INVENTION
As the device geometries shrink, the requirements for overlay and critical dimensions (CDs) become increasingly stringent and require more precision. In addition to the difficulty in achieving the accurate overlay, the ability to measure (by metrology tools) the feature size or overlay mark is beginning to reach the limits of optical detection techniques. Due to its limitations, optical metrology needs to be replaced by newer technologies.
The present invention seeks to provide a concept for replacing conventional optical overlay and CD metrology by a newer technique which mitigates or avoids the disadvantages and limitations of the prior art.


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Przybyla, J. et al., A Fully Integrated Photolithography Workcell, IEEE/SEMI International Semiconductor Manufacturing Science Symposium, 22-24 May, 1989, pp. 100-107, XP010085050, IEEE, New York.

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