Lithography correction method and device

Radiation imagery chemistry: process – composition – or product th – Including control feature responsive to a test or measurement

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

06783904

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to the field of semiconductors and more specifically to photolithography.
BACKGROUND OF THE INVENTION
As part of a semiconductor device manufacturing process, a photolithographic process is used to form a pattern in a photoresist layer on a semiconductor wafer by transferring light through a mask and lenses onto the photoresist layer. The pattern in the photoresist layer is transferred to an underlying layer (e.g., copper) on the semiconductor wafer to form a semiconductor device feature (e.g., an interconnect). However, the photolithography is a non-perfect pattern transfer process due to wave nature of light. Therefore, the patterns on the mask are often not transferred without error to the photoresist layer. Often this non-perfect pattern transfer results in smaller features than designed being printed, which is more severe for isolated features (features without other features in close proximity) than for dense features (features with other features in close proximity).
One proposed solution termed optical proximity correction (OPC) uses chosen lithographic process parameters (e.g., photoresist) so that the best overall result of dense and isolated features is achieved. To accommodate the processing problems, isolated features (or portions of isolated features) are enlarged relative to dense features (or portions of dense features) so that the isolated features print the width that they were designed to be. Therefore, the resulting pattern in the photolithographic process has the isolated features and dense features being the same width as they were designed. This can be achieved by enlarging the isolated features, decreasing the dense features or combinations of both. However, as semiconductor devices shrink, the designed width of features is often very difficult to pattern. Therefore, while OPC increases the ability to pattern isolated features, the ability to control etch processes and pattern small features in a photolithographic process is not sufficiently improved over using a photolithographic process without OPC.
Therefore, a need exists for a photolithographic process that allows for improved photolithographic patterning of isolated features and increased processing control of forming isolated and dense features in a sermiconductor manufacturing process.


REFERENCES:
patent: 5958635 (1999-09-01), Reich et al.
patent: 6120952 (2000-09-01), Pierrat et al.
patent: 6284419 (2001-09-01), Pierrat et al.
patent: 6319644 (2001-11-01), Pierrat et al.
patent: 1164432 (2001-12-01), None
McCallum, Some Lithographic Limits of Back End Lithography, Nikon Precision Europe GmbH. Nikon Court, Kirkton Campus, Livingston EH54 7DL, UK, 8 pgs (2001).

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