Lithographically optimized placement tool

Details Lithographically optimized placement tool Lithographically optimized placement tool

2006-03-09

2008-10-07

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07434188

ABSTRACT:
A system and a method are disclosed for integrating the results of lithographic simulation into the physical synthesis process. The effects of lithographic variation are considered when selecting a cell from among a group of cells having equivalent function. Circuit design elements are placed and routed with consideration of the effects of lithographic variation on robustness, timing performance, and leakage current. Cells may be simulated under a variety of conditions and environments and the simulation results stored in a library for efficient lithographically optimized placements.

REFERENCES:
patent: 6691297 (2004-02-01), Misaka et al.
patent: 6898769 (2005-05-01), Nassif et al.
patent: 2004/0010762 (2004-01-01), Habitz
patent: 2004/0107410 (2004-06-01), Misaka et al.

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