Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-11
2007-09-11
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10776901
ABSTRACT:
A method and system for layout optimization relative to lithographic process windows which facilitates lithographic constraints to be non-localized in order to impart a capability of printing a given circuit with a process window beyond the process windows which are attainable with conventional simplified design rules. Pursuant to the method and system, lithographic capability and process windows are maximized to satisfy local circuit requirements and in order to achieve a maximally efficient layout. In this connection, there is employed a method utilizing a generalized lithographic process window as a measure when layout optimization is extended to a degree beyond that achieved by the simple fixed design rules which are applied to the design rules obtained is the advantage that a lithographic process window is determined purely through the calculation of image intensities and slopes, and as a result, the method can be quite rapid in application because it is possible to take advantage of known methods for rapid calculation of image intensity, and because there is obviated the need for geometrical shape processing during optimization.
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Heng Fook-Luen
Lavin Mark A.
Lee Jin-Fuw
Ostapko Daniel L.
Rosenbluth Alan E.
Chiang Jack
Doan Nghia M.
Scully , Scott, Murphy & Presser, P.C.
Steinberq, Esq. William H.
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